參數(shù)資料
型號(hào)： AD9880KSTZ-150
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/64頁(yè)
文件大小： 0K
描述： IC INTERFACE/HDMI 150MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
配用： AD9880/PCBZ-ND - KIT EVALUATION AD9880
AD9880
Rev. 0 | Page 17 of 64
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOGIN input. The sync signal is extracted in a two step
process. First, the SOG input (typically 0.3 V below the black
level) is detected and clamped to a known dc voltage. Next, the
signal is routed to a comparator with a variable trigger level (set
by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the
clamped voltage. The sync slicer output is a digital composite
sync signal containing both Hsync and Vsync information (see
Figure 9).
AD9880
PLL CLOCK
GENERATOR
HSYNC FILTER
AND
REGENERATOR
HSYNC 0
SOG OUT
HSYNC
COAST
DATACK
SOGIN 0
COAST
CHANNEL
SELECT
VSYNC 1
ODD/EVEN
FIELD
MUX
RH3
FH4
SP5
MUX
1ACTIVITY DETECT
2POLARITY DETECT
3REGENERATED HSYNC
4FILTERED HSYNC
5SET POLARITY
SP5
AD1
PD2
AD1
PD2
AD1
PD2
SYNC
SLICER
SYNC
SLICER
VSYNC 0
HSYNC 1
HSYNC OUT
VSYNC OUT
SOGIN 1
HSYNC/VSYNC
COUNTER
REG 26H, 27H
SYNC
PROCESSOR
AND
VSYNC FILTER
MUX
PLL SYNC FILTER EN
0x21:6
SP SYNC FILTER EN
0x21:7
SOGOUT SELECT
0x24:2,1
[0x11:7]
HSYNC
SELECT
[0x11:3]
COAST SELECT
0x12:1
VSYNC FILTER EN
0x21:5
FILTER COAST VSYNC
0x12:0
VSYNC
FILTERED
VSYNC
05087-008
AD1
SP5
MUX
Figure 8. Sync Processing Block Diagram
04740-015
SOG INPUT
SOGOUT OUTPUT
CONNECTED TO
HSYNCIN
NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS
COMPOSITE
SYNC
AT HSYNCIN
VSYNCOUT
FROM SYNC
SEPARATOR
–300mV
700mV MAXIMUM
0mV
Figure 9. Sync Slicer and Sync Separator Output
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