參數(shù)資料
型號(hào)： AD9880KSTZ-150
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 37/64頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE/HDMI 150MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
配用： AD9880/PCBZ-ND - KIT EVALUATION AD9880
AD9880
Rev. 0 | Page 42 of 64
0x1B
5
Blue Clamp Select
This bit selects whether the blue channel is clamped to
ground or midscale. Ground clamping is used for blue
in RGB applications and midscale clamping is used in
YPrPb (YUV) applications.
Table 30. Blue Clamp
Select
Result
0
Channel clamped to ground during clamping period
1
Channel clamped to midscale during clamping period
The power-up default is 0.
0x1B
4
Clamp During Coast
This bit permits clamping to be disabled during
Coast. The reason for this is video signals are
generally not at a known backporch or midscale
position during Coast.
Table 31. Clamp During Coast
Select
Result
0
Clamping during Coast is disabled
1
Clamping during Coast is enabled
The power-up default is 0.
0x1B
3
Clamp Disable
Table 32. Clamp Disable
Select
Result
0
Internal clamp enabled
1
Internal clamp disabled
The power-up default is 0.
0x1B
2-1
Programmable Bandwidth
Table 33. Bandwidth
Select
Result
x0
Low bandwidth
x1
High bandwidth
The power-up default is 1.
0x1B
0
Hold Auto Offset
Table 34. Auto Offset Hold
Select
Result
0
Normal auto offset operation
1
Hold current offset value
The power-up default is 0.
0x1C
7
Auto Offset Enable
0 = manual offset
1 = auto offset using offset as target code. The power-
up default is 0.
0x1C
6-5
Auto Offset Update Mode
00 = every clamp
01 = every 16 clamps
10 = every 64 clamps
11 = every Vsync
The power-up default setting is 10.
0x1C
4-3
Difference Shift Amount
00 = 100% of difference used to calculate new offset
01 = 50%
10 = 25%
11 = 12.5%
The power-up default is 01.
0x1C
2
Auto Jump Enable
0 = normal operation
1 = if the code >15 codes off, the offset is jumped to
the predicted offset necessary to fix the >15 code mis-
match. The power-up default is 1.
0x1C
1
Post Filter Enable
The post filter reduces the update rate by 1/6 and
requires that all six updates recommend a change
before changing the offset. This prevents unwanted
offset changes.
0 = disable post filer
1 = enable post filter
The power-up default is 1.
0x1C
0
Toggle Filter Enable
The toggle filter looks for the offset to toggle back and
forth and holds it if triggered. This is to prevent
toggling in case of missing codes in the PGA.
1 = toggle filter on, 0 = toggle filter off.
The power-up default is 0.
0x1D
7-0
Slew Limit
Limits the amount the offset can change by in a single
update. The power-up default is 0x08.
0x1E
7-0
Sync Filter Lock Threshold
This 8-bit register is programmed to set the number
of valid Hsyncs needed to lock the sync filter. This
ensures that a consistent, stable Hsync is present
before attempting to filter. The power-up default
setting is 32d.
0x1F
7-0
Sync Filter Unlock Threshold
This 8-bit register is programmed to set the number of
missing or invalid Hsyncs needed to unlock the sync
filter. This disables the filter operation when there is
no longer a stable Hsync signal. The power-up default
setting is 50d.
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