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參數(shù)資料
| 型號： | AD9880KSTZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/HDMI 150MHZ 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬，HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | AD9880/PCBZ-ND - KIT EVALUATION AD9880 |
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AD9880
Rev. 0 | Page 30 of 64
Hex
Address
Read/Write
or Read Only
Bits
Default
Value
Register Name
Description
0x50
Read/Write
[7:0]
00100000
Test
Must be written to 0x20 for proper operation.
0x56
Read/Write
[7:0]
00001111
Test
Must be written to default 0x0F for proper operation.
0x57
Read/Write
[7]
0*******
A/V Mute Override
A1 overrides the AV mute value with Bit 6.
[6]
*0******
AV Mute Value
Sets AV mute value if override is enabled.
[3]
****0***
Disable Video Mute
Disables mute of video during AV mute.
[2]
*****0**
Disable Audio Mute
Disables mute of audio during AV mute.
0x58
Read/Write
[7]
MCLK PLL Enable
MCLK PLL enable—uses analog PLL.
[6:4]
MCLK PLL_N
MCLK PLL N [2:0]—this controls the division of the MCLK out of
the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4, etc.
[3]
N_CTS_Disable
Prevents the N/CTS packet on the link from writing to the N and
CTS registers.
[2:0]
MCLK FS_N
Controls the multiple of 128 fs used for MCLK out . 0 = 128 fs,
1 = 256 fs, 2 = 384, 7 = 1024 fs.
0x59
Read/Write
[6]
MDA/MCL PU
This disables the MDA/MCL pull-ups.
[5]
CLK Term O/R
Clock termination power-down override 0 = auto, 1 = manual.
[4]
Manual CLK Term
Clock termination: 0 = normal, 1 = disconnected.
[2]
FIFO Reset UF
This bit resets the audio FIFO if underflow is detected.
[1]
FIFO Reset OF
This bit resets the audio FIFO if overflow is detected.
[0]
MDA/MCL Three-
State
This bit three-states the MDA/MCL lines.
0x5A
Read
[6:0]
Packet Detected
These 7 bits are updated if any specific packet has been received
since last reset or loss of clock detect. Normal is 0x00.
Bit
Data Packet Detected
0
AVI infoframe.
1
Audio infoframe.
2
SPD infoframe.
3
MPEG source infoframe.
4
ACP packets.
5
ISRC1 packets.
6
ISRC2 packets.
0x5B
Read
[3]
HDMI Mode
0 = DVI, 1 = HDMI.
0x5E
Read
[7:6]
Channel Status
Mode = 00. All others are reserved.
[5:3]
When Bit 1 = 0 (Linear PCM).
000 = 2 audio channels without pre-emphasis.
001 = 2 audio channels with 50/15 μs pre-emphasis.
010 = reserved.
011 = reserved.
2
0 = Software for which copyright is asserted.
1 = Software for which no copyright is asserted.
1
0 = audio sample word represents linear PCM samples.
1 = audio sample word used for other purposes.
0
0 = consumer use of channel status block.
Audio Channel Status
0x5F
Read
[7:0]
Channel Status
Category Code
0x60
Read
[7:4]
Channel Number
[3:0]
Source Number
0x61
Read
[5:4]
Clock Accuracy
Clock accuracy.
00
= Level II.
01
= Level III.
10
= Level I.
11
= reserved.
[3:0]
Sampling
0011
=
32 kHz.
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