參數(shù)資料
型號(hào)： AD9880KSTZ-150
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/64頁(yè)
文件大小： 0K
描述： IC INTERFACE/HDMI 150MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
配用： AD9880/PCBZ-ND - KIT EVALUATION AD9880
AD9880
Rev. 0 | Page 41 of 64
0x15
1
Coast Detection Bit
This bit detects activity on the EXTCLK/EXTCOAST
pin. It indicates that one of the two signals is active,
but it doesn’t indicate if it is EXTCLK or EXTCOAST.
A dc signal is not detected.
Table 21. Coast Detection Results
Detect
Result
0
No activity detected
1
Activity detected
POLARITY STATUS
0x16
7
Hsync0 Polarity
Indicates the polarity of the Hsync0 input.
Table 22. Detected Hsync0 Polarity Results
Detect
Result
0
Hsync polarity negative
1
Hsync polarity positive
0x16
6
Hsync 1 Polarity
Indicates the polarity of the Hsync1 input.
Table 23. Detected Hsync1 Polarity Result
Detect
Result
0
Hsync polarity negative
1
Hsync polarity positive
0x16
5
Vsync0 Polarity
Indicates the polarity of the Vsync0 input.
Table 24. Detected Vsync0 Polarity Results
Detect
Result
0
Vsync polarity negative
1
Vsync polarity Positive
0x16
4
Vsync1 Polarity
Indicates the polarity of the Vsync1 input.
Table 25. Detected Vsync 1 Polarity Results
Detect
Result
0
Vsync polarity negative
1
Vsync polarity positive
0x16
3 Coast Polarity
Indicates the polarity of the external Coast signal.
Table 26. Detected Coast Polarity Results
Detect
Result
0
Coast polarity negative
1
Coast polarity positive
0x16
2
Pseudo Sync Detected
0x16
1
Sync Filter Locked
Indicates whether sync filter is locked to periodic sync
signals. 0 = sync filter locked to periodic sync signal.
1 = sync filter not locked.
Table 27. Sync Filter Lock Detect
Detect
Result
0
Sync filter locked to periodic sync signal
1
Sync filter not locked to periodic sync signal
0x16
0
Bad Sync Detect
0x17
3-0
Hsyncs per Vsync MSBs
The 4 MSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input. This is
useful in determining the mode and an aid in setting
the PLL divide ratio.
0x18
7-0
Hsyncs per Vsync LSBs
The 8 LSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input.
0x19
7-0
Clamp Placement
Number of pixel clocks after trailing edge of Hsync to
begin clamp. The power-up default is 8.
0x1A
7-0
Clamp Duration
Number of pixel clocks to clamp. The power-up
default is 0x14.
0x1B
7
Red Clamp Select
This bit selects whether the red channel is clamped to
ground or midscale. Ground clamping is used for red
in RGB applications and midscale clamping is used in
YPrPb (YUV) applications.
Table 28. Red Clamp
Select
Result
0
Channel clamped to ground during clamping period
1
Channel clamped to midscale during clamping period
The power-up default is 0.
0x1B
6
Green Clamp Select
This bit selects whether the green channel is clamped
to ground or midscale. Ground clamping is normally
used for green in RGB applications and YPrPb (YUV)
applications.
Table 29. Green Clamp
Select
Result
0
Channel clamped to ground during clamping period
1
Channel clamped to midscale during clamping period
The power-up default is 0.
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