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參數(shù)資料
| 型號： | AD9880KSTZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/HDMI 150MHZ 100LQFP |
| 標準包裝： | 1 |
| 應用： | 視頻 |
| 接口： | 模擬，HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | AD9880/PCBZ-ND - KIT EVALUATION AD9880 |
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AD9880
Rev. 0 | Page 37 of 64
2-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
0x00
7-0
Chip Revision
An 8-bit value that reflects the current chip revision.
PLL DIVIDER CONTROL
0x01
7-0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide
ratio PLLDIV.
The PLL derives a pixel clock from the incoming
Hsync signal. The pixel clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 221 to 4095. The higher the value loaded
in this register, the higher the resulting clock
frequency with respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications, which assists in determining the value
for PLLDIV as a function of horizontal and vertical
display resolution and frame rate (see Table 8).
However, many computer systems do not conform
precisely to the recommendations, and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV usually produces one or more vertical noise
bars on the display. The greater the error, the greater
the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx)
The AD9880 updates the full divide ratio only when
the LSBs are changed. Writing to this register by itself
does not trigger an update.
0x02
7-4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide
ratio PLLDIV.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
CLOCK GENERATOR CONTROL
0x03
7-6
VCO Range Select
Two bits that establish the operating range of the clock
generator. VCORNGE must be set to correspond with
the desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre-
quencies. For this reason, to output low pixel rates and
still get good jitter performance, the PLL actually
operates at a higher frequency but then divides down
the clock rate. Table 12 shows the pixel rates for each
VCO range setting. The PLL output divisor is auto-
matically selected with the VCO range setting.
Table 12. VCO Ranges
VCO Range
Pixel Rate Range
00
12 to 30
01
30 to 60
10
60 to 120
11
120 to 150
The power-up default value is 01.
5-3
Charge Pump Current
Three bits that establish the current driving the loop
filter in the clock generator.
Table 13. Charge Pump Currents
Ip2
Ip1
Ip0
Current (μA)
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
The power-up default value is current = 001.
2
External Clock Enable
This bit determines the source of the pixel clock.
Table 14. External Clock Select Settings
EXTCLK
Function
0
Internally generated clock.
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external CKEXT input pin. In
this mode, the PLL divide ratio (PLLDIV) is ignored.
The clock phase adjusts (phase is still functional). The
power-up default value is EXTCLK = 0.
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