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參數資料
| 型號： | AD9880KSTZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 19/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/HDMI 150MHZ 100LQFP |
| 標準包裝： | 1 |
| 應用： | 視頻 |
| 接口： | 模擬，HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | AD9880/PCBZ-ND - KIT EVALUATION AD9880 |
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AD9880
Rev. 0 | Page 26 of 64
Hex
Address
Read/Write
or Read Only
Bits
Default
Value
Register Name
Description
[6]
*1******
PLL Sync Filter Enable
Enables the PLL to use the filtered Hsync rather than the raw
Hsync. This clips any bad Hsyncs, but does not regenerate
missing pulses.
[5]
**0*****
Vsync Filter Enable
Enables the Vsync filter. The Vsync filter gives a predictable
Hsync/Vsync timing relationship but clips one Hsync period off
the leading edge of Vsync.
[4]
***0****
Vsync Duration
Enable
Enables the Vsync duration block. This block can be used if
necessary to restore the duration of a filtered Vsync.
[3]
**** 1***
Auto Offset Clamp
Mode
0 = auto offset measures code during clamp.
1 = auto offset measures code (10 or 16) clock cycles after end of
clamp for 6 clock cycles.
[2]
**** *1**
Auto Offset Clamp
Length
Sets delay after end of clamp for auto offset clamp mode = 1.
0 = Delay is 10 clock cycles.
1 = Delay is 16 clock cycles.
0x22
Read/Write
[7:0]
4
Vsync Duration
Vsync Duration.
0x23
Read/Write
[7:0]
32
Hsync Duration
Hsync Duration. Sets the duration of the output Hsync in pixel
clocks.
0x24
Read/Write
[7]
1*******
Hsync Output
Polarity
Output Hsync Polarity (both DVI and Analog). 0 = active low out.
1 = active high out.
[6]
*1******
Vsync Output Polarity
Output Vsync polarity (both DVI and analog).
0 = active low out.
1 = active high out.
[5]
**1*****
DE Output Polarity
Output DE polarity (both DVI and analog) .
0 = active low out.
1 = active high out.
[4]
***1****
Field Output Polarity
Output field polarity (both DVI and analog).
0 = active low out.
1 = active high out.
[3]
****1***
SOG Output Polarity
Output SOG polarity (analog only).
0 = active low out.
1 = active high out.
[2:1]
*****11*
SOG Output Select
Selects signal present on SOG output.
00 = SOG (SOG0 or SOG1).
01 = Raw Hsync (HSYNC0 or HSYNC1).
10 = Regenerated sync.
11 = Hsync to PLL.
[0]
*******0
Output CLK Invert
0 = Don’t invert clock out.
1 = Invert clock out.
0x25
Read/Write
[7:6]
01******
Output CLK Select
Select which clock to use on output pin. 1× CLK is divided down
from TMDS clock input when pixel repetition is in use.
00 = × CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1X CLK.
[5:4]
**11****
Output Drive
Strength
Set the drive strength of the outputs.
00 = lowest, 11 = highest.
[3:2]
****00**
Output Mode
Selects which pins the data comes out on.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
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