參數(shù)資料
型號： AD9852ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 5/52頁
文件大?。?/td> 0K
描述： IC DDS SYNTHESIZER CMOS 80-LQFP
產(chǎn)品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1
分辨率（位）： 12 b
主 fclk： 200MHz
調節(jié)字寬（位）： 48 b
電源電壓： 3.14 V ~ 3.47 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
配用： AD9852/PCBZ-ND - BOARD EVAL FOR AD9852
AD9852
Rev. E | Page 13 of 52
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the
internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of sampling
the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which
effectively lowers the noise floor.
0
CENTER 39.1MHz
–10
–20
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–40
–50
–60
–70
–80
–90
–100
100kHz/
SPAN 1MHz
00634-010
Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00634-011
Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00634-012
Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100kHz/
SPAN 1MHz
00634-013
Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00634-014
Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00634-015
Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
10 MHz REFCLK with REFCLK Multiplier = 10×
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相關代理商/技術參數(shù)
參數(shù)描述
AD9852ASTZ 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80
AD9852ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
AD9852ASVZ 功能描述:IC DDS SYNTHESIZER CMOS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9852ASVZ 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80
AD9852ASVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
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