參數資料
型號: AD9953YSVZ
廠商: Analog Devices Inc
文件頁數: 1/32頁
文件大?。?/td> 0K
描述: IC DDS DAC 14BIT 400MSPS 48-TQFP
產品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝: 1
分辨率(位): 14 b
主 fclk: 400MHz
調節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
產品目錄頁面: 552 (CN2011-ZH PDF)
400 MSPS, 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9953
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2004–2009 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile VHF/UHF LO frequency synthesis
FM chirp source for radar and scanning systems
Nonlinear-shaped PSK/FSK modulator
Test and measurement equipment
FUNCTIONAL BLOCK DIAGRAM
1024
× 32
STATIC RAM
COS(X)
CONTROL REGISTERS
OSCILLATOR/BUFFER
SYNC
ENABLE
I/O UPDATE
Z–1
OSK
PWRDWNCTL
REFCLK
CRYSTAL OUT
I/O PORT
PS<1:0>
RAM DATA <31:18>
FRE
Q
UE
NCY
TUNING
WORD
RAM
DATA
DDS
CLOCK
DDS
CLOCK
P
HAS
E
ACCUMULATOR
R
ESET
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
DAC_RSET
DDS CORE
PHASE
OFFSET
PHASE
ACCUMULATOR
Z–1
IOUT
RAM
DATA
DAC
SYNC_IN
PHASE
OFFSET
WORD
SYNC_CLK
RESET
TIMING AND CONTROL LOGIC
4
×–20×
CLOCK
MULTIPLIER
÷ 4
AD9953
32
14
32
R
A
M
A
D
R
E
S
10
RAM
CONTROL
3
19
14
0
M
U
X
32
M
U
X
M
U
X
03357-0-001
Figure 1.
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