參數(shù)資料
型號(hào)： AD9852ASTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 0K
描述： IC DDS SYNTHESIZER CMOS 80-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 12 b
主 fclk： 200MHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 3.14 V ~ 3.47 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9852/PCBZ-ND - BOARD EVAL FOR AD9852
AD9852
Rev. E | Page 24 of 52
supplied or internally generated. See the Internal and External
Update Clock section for a discussion of the I/O update.
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)
is available to clear both the frequency accumulator (ACC1)
and the phase accumulator (ACC2). When this bit is set high,
the output of the phase accumulator results in 0 Hz output from
the DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
the previous DDS operation, CLR ACC2 must be set to logic
low. This bit is useful for generating pulsed FM.
Figure 43 graphically illustrates the effect of the CLR ACC2 bit on
the DDS output frequency. Reprogramming the registers while
the CLR ACC2 bit is high allows a new FTW1 frequency and
slope to be loaded.
Another function only available in the chirp mode is the
HOLD pin (Pin 29). This function stops the clock signal to the
ramp rate counter, thereby halting any further clocking pulses
to the frequency accumulator, ACC1.
The effect is to halt the chirp at the frequency existing just
before the HOLD pin is pulled high. When the HOLD pin is
returned low, the clock resumes and chirp continues. During a
hold condition, the user can change the programming registers;
however, the ramp rate counter must resume operation at its
previous rate until a count of 0 is obtained before a new ramp
rate count can be loaded. Figure 44 illustrates the effect of the
hold function on the DDS output frequency.
I/O UD CLK
F1
0
FREQUENCY
MODE
FTW1
DFW
F1
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
DELTA FREQUENCY WORD
CLR ACC1
00634-042
Figure 42. Effect of CLR ACC1 in FM Chirp Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9852ASTZ 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80
AD9852ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
AD9852ASVZ 功能描述:IC DDS SYNTHESIZER CMOS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9852ASVZ 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80
AD9852ASVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
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