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參數(shù)資料
| 型號： | AD9852ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/52頁 |
| 文件大小： | 0K |
| 描述： | IC DDS SYNTHESIZER CMOS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 200MHz |
| 調(diào)節(jié)字寬（位）： | 48 b |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9852/PCBZ-ND - BOARD EVAL FOR AD9852 |
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AD9852
Rev. E | Page 35 of 52
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Table 12.
Pin
Description
SCLK
Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state
machines. The SCLK maximum frequency is 10 MHz.
CS
Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and
SDIO pins go to a high impedance state when this input is high. If this pin is driven high during a communication cycle, the
cycle is suspended until CS is reactivated low. The chip select pin can be tied low in systems that maintain control of SCLK.
SDIO
Serial Data I/O (Pin 19). Data is always written to the AD9852 on this pin. However, this pin can be used as a bidirectional data
line. The configuration of this pin is controlled by Bit 0 of Register Address 20 hex. The default is Logic 0, which configures the
SDIO pin as bidirectional.
SDO
Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data.
In the case where the AD9852 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high
impedance state.
IO RESET
Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable
registers. An active high input on the IO RESET pin causes the current communication cycle to terminate. After the IO RESET pin
returns low (Logic 0), another communication cycle can begin, starting with the instruction byte.
Notes on Serial Port Operation
The AD9852 serial port configuration bits reside in Bit 1 and Bit 0
of Register Address 20 hex. The configuration changes immediately
upon a valid I/O update. For multibyte transfers, writing to this
register can occur during the middle of a communication cycle.
Care must be taken to compensate for this new configuration
during the remainder of the current communication cycle.
The system must maintain synchronization with the AD9852;
otherwise, the internal control logic is not able to recognize further
instructions. For example, if the system sends the instruction to
write a 2-byte register and then pulses the SCLK pin for a 3-byte
register (24 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising
edges after the instruction cycle properly write the first two data
bytes into the AD9852, but the subsequent eight rising SCLK
edges are interpreted as the next instruction byte, not the final
byte of the previous communication cycle.
In cases where synchronization is lost between the system and
the AD9852, the IO RESET pin provides a means to re-establish
synchronization without reinitializing the entire chip. Asserting
the IO RESET pin (active high) resets the AD9852 serial port
state machine, terminating the current I/O operation and forcing
the device into a state in which the next eight SCLK rising edges
are understood to be an instruction byte. The IO RESET pin
must be deasserted (low) before the next instruction byte write
can begin. Any information written to the AD9852 registers
nization remains intact.
MSB/LSB TRANSFERS
The AD9852 serial port can support both MSB- and LSB-first
data formats. This functionality is controlled by Bit 1 of Serial
Bank 20 hex. When this bit is set active high, the AD9852 serial
port is in LSB-first format. This bit defaults low, to the MSB-first
format. The instruction byte must be written in the format
indicated by Bit 1 of Serial Register Bank 20 hex. Therefore, if
the AD9852 is in LSB-first mode, the instruction byte must be
written from LSB to MSB.
CS
SCLK
SDIO
tPRE
tDSU
tSCLKPWH tSCLKPWL
tSCLK
tDHLD
SECOND BIT
FIRST BIT
SYMBOL
tPRE
tSCLK
tDSU
tSCLKPWH
tSCLKPWL
tDHLD
MIN
30ns
100ns
30ns
40ns
0ns
DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK
SERIAL DATA SETUP TIME
SERIAL DATA CLOCK PULSE WIDTH HIGH
SERIAL DATA CLOCK PULSE WIDTH LOW
SERIAL DATA HOLD TIME
00634-053
Figure 53. Timing Diagram for Data Write to AD9852
tDV
FIRST BIT
SECOND BIT
SDIO
SDO
SCLK
CS
SYMBOL
tDV
MAX
30ns
DEFINITION
DATA VALID TIME
00634-054
Figure 54. Timing Diagram for Read from AD9852
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852ASTZ | 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80 |
| AD9852ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852ASVZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
| AD9852ASVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
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