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| 型號： | AD9548BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 65/112頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 帶卷 (TR) |
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AD9548
Data Sheet
Rev. E | Page 56 of 112
IC SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two
control pins and is a de facto standard throughout the I2C
industry. However, its disadvantage is programming speed, which
is 400 kbps maximum. The AD9548 I2C port design is based on
the I2C fast mode standard from Philips, so it supports both the 100
kHz standard mode and 400 kHz fast mode. Fast mode imposes a
glitch tolerance requirement on the control signals. That is, the
input receivers ignore pulses of less than 50 ns duration.
The AD9548 I2C port consists of a serial data line (SDA) and a
serial clock line (SCL). In an I2C bus system, the AD9548 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9548.
The AD9548 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9548 allows up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address
transmitted as part of an I2C packet. Only the device with a
matching slave address responds to subsequent I2C commands.
The device slave address is 1001xxx (the three right bits are
determined by the M0 to M2 pins). The four MSBs (1001) are
hard-wired, while the three LSBs (xxx, determined by the M0 to
M2 pins) are programmable via the power-up state of the
multifunction pins (see the Initial Pin Programming section).
I2C Bus Characteristics
Table 34. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
Nonacknowledge
W
Write
R
Read
The transfer of data is shown in Figure 61. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can only change when the
clock signal on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
0
802
2-
0
35
SDA
SCL
Figure 61. Valid Bit Transfer
Start/stop functionality is shown in Figure 62. The start condition
is characterized by a high-to-low transition on the SDA line
while SCL is high. The start condition is always generated by
the master to initialize a data transfer. The stop condition is
characterized by a low-to-high transition on the SDA line while
SCL is high. The stop condition is always generated by the
master to terminate a data transfer. Every byte on the SDA line
must be eight bits long. Each byte must be followed by an
acknowledge bit; bytes are sent MSB first.
SDA
START CONDITION
STOP CONDITION
SCL
S
P
0
8022
-03
6
Figure 62. Start and Stop Conditions
12
89
12
3 TO 7
89
10
SDA
SCL
S
MSB
ACK FROM
SLAVE-RECEIVER
ACK FROM
SLAVE-RECEIVER
P
08
02
2-
03
7
Figure 63. Acknowledge Bit
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| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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