參數(shù)資料
型號： AD9548BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 39/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 400
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 帶卷 (TR)
AD9548
Data Sheet
Rev. E | Page 32 of 112
Phase Build-Out Reference Switching
Phase build-out reference switching is the term given to a
reference switchover that completely masks any phase
difference between the previous reference and the new
reference. That is, there is virtually no phase change detectable
at the output when a phase build-out switchover occurs.
The AD9548 handles phase build-out switching based on
whether the new reference is a phase master. A phase master is
any reference with a selection priority value that is less than the
phase master threshold priority value (that is, higher priority).
The phase master threshold priority value resides in the phase
build-out switching register (Address 0x0507), whereas the
selection priority resides in the profile registers (Address 0x0600
to Address 0x07FF). By default, the phase master threshold
priority is 0; therefore, no references can be phase masters
until the user changes the phase master threshold priority.
Whenever the AD9548 switches from one reference to another,
it compares the selection priority value stored in the profile
assigned to the new reference with the phase master threshold
priority. The AD9548 performs a phase build-out switchover
only if the new reference is not a phase master.
Hitless Reference Switching (Phase Slew Control)
Hitless reference switching is the term given to a reference
switchover that limits the rate of change of the phase of the
output clock while the PLL is in the process of acquiring phase
lock. This prevents the output frequency offset from becoming
excessive.
The all-digital nature of the DPLL core (see the Digital PLL
(DPLL) Core section) gives the user numerical control of the
rate at which phase changes occur at the DPLL output. When
enabled, a phase slew controller monitors the phase difference
between the feedback and reference inputs to the DPLL. The
phase slew controller has the ability to place a user specified
limit on the rate of change of phase, thus providing a
mechanism for hitless reference switching.
The user sets a limit on the rate of change of phase by storing
the appropriate value in the 16-bit phase slew rate limit register
(Address 0x0316 to Address 0x0317). The 16-bit word
(representing ns/sec) puts an upper bound on the rate of change
of the phase at the output of the DPLL during a reference
switchover. A phase slew rate value of 0 (default) disables the
phase slew controller.
The accuracy of the phase slew controller depends on both the
phase slew limit value and the system clock frequency.
Generally, an increase in the phase slew rate limit value or a
decrease in the system clock frequency tends to reduce the
error. As such, the accuracy is best for the largest phase slew
limit value and the lowest system clock frequency. For example,
assuming the use of a 1 GHz system clock, a phase slew limit
value of 315 ns/sec (or more) ensures an error of less than 10%,
whereas a phase slew rate limit value above ~3100 ns/sec
ensures an error of less than 1%. On the other hand, assuming
the use of a 500 MHz system clock, the same phase slew rate
limit values ensure an error of less than 5% or 0.5%,
respectively.
DIGITAL PLL (DPLL) CORE
DPLL Overview
A diagram of the digital PLL core of the AD9548 appears in
Figure 38. The phase/frequency detector, feedback path, lock
detectors, phase offset, and phase slew rate limiting that
comprise this second generation DPLL are all digital
implementations.
R + 1
REF A
TDC
AND
PFD
DIGITAL
LOOP
FILTER
DDS/
DAC
DACOUT
CLOSED-LOOP
PHASE OFFSET
PHASE SLEW
LIMIT
LOCK
DETECT
REF DD
DPPL CORE
2
fR
fTDC
fDDS
S + 1 + U/V
08022-
013
Figure 38. Digital PLL Core
The start of the DPLL signal chain is the reference signal, fR,
which is the frequency of the reference input. A reference
prescaler reduces the frequency of this signal by an integer factor,
R + 1, where R is the 30-bit value stored in the appropriate
profile register and 0 ≤ R ≤ 1,073,741,823. Therefore, the fre-
quency at the output of the R-divider (or the input to TDC) is
1
+
=
R
f
R
TDC
A time-to-digital converter (TDC) samples the output of the
R-divider. The TDC/PFD produces a time series of digital
words and delivers them to the digital loop filter. The digital
loop filter offers the following advantages:
Determination of the filter response by numeric
coefficients rather than by discrete component values
The absence of analog components (R/L/C), which
eliminates tolerance variations due to aging
The absence of thermal noise associated with analog
components
The absence of control node leakage current associated
with analog components (a source of reference feed-
through spurs in the output spectrum of a traditional
analog PLL)
The digital loop filter produces a time series of digital words at
its output and delivers them to the frequency tuning input of a
DDS, with the DDS replacing the function of the VCO in an
analog PLL. The digital words from the loop filter tend to steer
the DDS frequency toward frequency and phase lock with the
input signal (fTDC). The DDS provides an analog output signal
via an integrated DAC, effectively mimicking the operation of
an analog VCO.
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