參數(shù)資料
型號： AD9548BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 108/112頁
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 400
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 帶卷 (TR)
Data Sheet
AD9548
Rev. E | Page 95 of 112
Register 0x0A03—ResetFunc
Table 122. Reset Functions1
Address
Bits
Bit Name
Description
0x0A03
[7]
Unused
[6]
Clear LF
Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool).
[5]
Clear CCI
Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
[4]
Clear phase
accumulator
Setting this bit (default = 0) clears DDS phase accumulator (not a recommended
action).
[3]
Reset auto sync
Setting this bit (default = 0) resets the automatic synchronization logic
(see Register 0x0403).
[2]
Reset TW history
Setting this bit (default = 0) resets the tuning word history logic (part of holdover
functionality).
[1]
Reset all IRQs
Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0x0D02 to
Register 0x0D09). It is the equivalent of setting all the bits of the IRQ clearing register
(Register 0x0A04 to Register 0x0A0B).
[0]
Reset watchdog
Setting this bit (default = 0) resets the watchdog timer (see Register 0x0211 to
Register 0x0212). If the timer had timed out, it simply starts a new timing cycle. If the
timer has not yet timed out, it restarts at time zero without causing a timeout event.
Continuously resetting the watchdog timer at intervals less than its timeout period
prevents the watchdog timer from generating a timeout event.
1
All bits in this register are autoclearing.
Register 0x0A04 to Register 0x0A0B—IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0x0D02 to Address 0x0D09). When set to Logic
1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 123. IRQ Clearing for SYSCLK
Address
Bits
Bit Name
Description
0x0A04
[7:6]
Unused
[5]
SYSCLK unlocked
Clears SYSCLK unlocked IRQ
[4]
SYSCLK locked
Clears SYSCLK locked IRQ
[3:2]
Unused
[1]
SYSCLK Cal complete
Clears SYSCLK calibration complete IRQ
[0]
SYSCLK Cal started
Clears SYSCLK calibration started IRQ
Table 124. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bits
Bit Name
Description
0x0A05
[7:4]
Unused
[3]
Distribution sync
Clears distribution sync IRQ
[2]
Watchdog timer
Clears watchdog timer IRQ
[1]
EEPROM fault
Clears EEPROM fault IRQ
[0]
EEPROM complete
Clears EEPROM complete IRQ
Table 125. IRQ Clearing for the Digital PLL
Address
Bits
Bit Name
Description
0x0A06
[7]
Switching
Clears switching IRQ
[6]
Closed
Clears closed IRQ
[5]
Freerun
Clears freerun IRQ
[4]
Holdover
Clears holdover IRQ
[3]
Freq unlocked
Clears frequency unlocked IRQ
[2]
Freq locked
Clears frequency locked IRQ
[1]
Phase unlocked
Clears phase unlocked IRQ
[0]
Phase locked
Clears phase locked IRQ
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