參數(shù)資料
型號： AD9548BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 59/112頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 400
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 帶卷 (TR)
AD9548
Data Sheet
Rev. E | Page 50 of 112
Table 28 lists a sample EEPROM download instruction sequence.
It illustrates the use of condition instructions and how they alter
the download sequence. The table begins with the assumption
that no conditions are in effect. That is, the most recently executed
condition instruction is 0xB0 or no conditional instructions
have been processed.
Table 28. EEPROM Conditional Processing Example
Instruction
Action
0x08
Transfer the system clock register contents
regardless of the current condition.
0x01
0x00
0xB1
Tag Condition 1
0x19
Transfer the clock distribution register contents
only if condition = 1
0x04
0x00
0xB2
Tag Condition 2
0xB3
Tag Condition 3
0x07
Transfer the reference input register contents only
if condition = 1, 2, or 3
0x05
0x00
0x0A
Calibrate the system clock only if condition = 1, 2,
or 3
0xB0
Clear the condition tag board
0x80
Execute an I/O update regardless of the value of
the condition
0x0A
Calibrate the system clock regardless of the value
of the condition
Storing Multiple Device Setups in EEPROM
Conditional processing makes it possible to create a number of
different device setups, store them in EEPROM, and download
a specific setup on demand. To do so, first program the device
control registers for a specific setup. Then, store an upload
sequence in the EEPROM scratch pad with the following
general form:
1. Condition instruction (0xB1 to 0xCF) to identify the setup
with a specific condition (1 to 31)
2. Data instructions (to save the register contents) along with
any required calibrate and/or I/O update instructions
3. Pause instruction (0xFE)
With the upload sequence written to the scratch pad, perform
an EEPROM upload (Register 0x0E02, Bit 0).
Reprogram the device control registers for the next desired
setup. Then store a new upload sequence in the EEPROM
scratch pad with the following general form:
1. Condition instruction (0xB0)
2. The next desired condition instruction (0xB1 to 0xCF, but
different than the one used during the previous upload to
identify a new setup)
3. Data instructions (to save the register contents) along with
any required calibrate and/or I/O update instructions
4. Pause instruction (FE)
With the upload sequence written to the scratch pad, perform
an EEPROM upload (Register 0x0E02, Bit 0).
Repeat the process of programming the device control registers
for a new setup, storing a new upload sequence in the EEPROM
scratch pad (Step 1 through Step 4), and executing an EEPROM
upload (Register 0x0E02, Bit 0) until all of the desired setups
have been uploaded to the EEPROM.
Note that, on the final upload sequence stored in the scratch
pad, the pause instruction (FE) must be replaced with an end
instruction (FF).
To download a specific setup on demand, first store the condition
associated with the desired setup in Register 0x0E01, Bits[4:0].
Then perform an EEPROM download (Register 0x0E03, Bit 1).
Alternatively, to download a specific setup at power-up, apply the
required logic levels necessary to encode the desired condition on
the M3 to M7 multifunction pins. Then power up the device; an
automatic EEPROM download occurs. The condition (as
established by the M3 to M7 multifunction pins) guides the
download sequence and results in a specific setup.
Keep in mind that the number of setups that can be stored
in the EEPROM is limited. The EEPROM can hold a total of
2048 bytes. Each nondata instruction requires one byte of
storage. Each data instruction, however, requires N + 4 bytes of
storage, where N is the number of transferred register bytes and
the other four bytes include the data instruction itself (one
byte), the target address (two bytes), and the checksum
calculated by the EEPROM controller during the upload
sequence (one byte).
Programming the EEPROM to Include a Clock Part ID
A special EEPROM loading sequence is required to use the
clock part ID registers. These registers provide for part and
revision identification.
The default EEPROM loading sequence from Register 0x0E10
to Register 0x0E31 is unchanged. The following steps must be
inserted into the EEPROM storage sequence to use the clock
part ID registers:
1. Register 0x0E32 = 0x07 (write 8 bytes)
2. Register 0x0E33 = 0x0C (at Register 0x0C00)
3. Register 0x0E34 = 0x00
4. Register 0x0E35 = 0x80 (I/O update)
5. Register 0x0E36 = 0xFF (end of data)
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