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參數(shù)資料
| 型號(hào)： | AD9548BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 帶卷 (TR) |
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AD9548
Data Sheet
Rev. E | Page 52 of 112
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9548 uses the bidirectional MSB-first mode. The reason that
bidirectional is the default mode is so that the user can still
write to the device, if it is wired for unidirectional operation, to
switch to unidirectional mode.
Assertion (active low) of the CS pin initiates a write or read
operation to the AD9548 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the CS stalled high mode (see Table 30). In this mode,
the CS pin can be temporarily deasserted on any byte boundary,
allowing time for the system controller to process the next
byte. CS can be deasserted only on byte boundaries, however.
This applies to both the instruction and data portions of the
transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, then the state machine must
be reset by either completing the transfer or by asserting the CS
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the CS pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In the streaming mode (see Table 30), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented. CS must be
deasserted at the end of the last byte transferred, thereby ending
the stream mode.
Table 30. Byte Transfer Count
W1
W0
Bytes to Transfer
0
1
0
1
2
1
0
3
1
Streaming mode
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two-part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9548 serial control port with information
regarding the payload. The instruction word includes the R/W
bit that indicates the direction of the payload transfer (that is, a
read or write operation). The instruction word also indicates
the number of bytes in the payload and the starting register
address of the first payload byte.
Write
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9548. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (1, 2, or 3 bytes or streaming mode) depends on the W0
and W1 bits (see Table 30) in the instruction byte. When not
streaming, CS can be deasserted after each sequence of eight
bits to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes
when CS is asserted. Deasserting the CS pin on a nonbyte
boundary resets the serial control port. Reserved or blank
registers are not skipped over automatically during a write
sequence. Therefore, the user must know what bit pattern to
write to the reserved registers to preserve proper operation of
the part. Generally, it does not matter what data is written to blank
registers, but it is customary to write 0s.
Most of the serial port registers are buffered (see the
Buffered/Active Registers section for details on the difference
between buffered and active registers). Therefore, data written
into buffered registers does not take effect immediately. An
additional operation is needed to transfer buffered serial control
port contents to the registers that actually control the device.
This is accomplished with an I/O update operation, which is
performed in one of two ways. One is by writing a Logic 1 to
Register 0x0005, Bit 0 (this bit is self-clearing). The other is to
use an external signal via an appropriately programmed
multifunction pin. The user can change as many register bits as
desired before executing an I/O update. The I/O update operation
transfers the buffer register contents to their active register
counterparts.
Read
The AD9548 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word. N is the number of data bytes read and
depends on the W0 and W1 bits of the instruction word.
During a SPI read, serial data on SDIO (or SDO in the case
of 4-wire mode) transitions on the SCLK falling edge, and is
normally sampled on the SCLK rising edge. To read the last bit
correctly, the SPI host must be able to tolerate a zero hold time. If
zero hold time is not possible, the user can either use streaming
mode and delay the rising edge of CS, or sample the serial data on
the SCLK falling edge. However, to sample the data on the
SCLK falling edge correctly, the user must ensure that the setup
time is greater than tDV (time data valid). Blank registers are not
skipped over during readback.
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x0004, Bit 0.
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| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
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| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9549ABCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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