參數(shù)資料
型號: AD9547BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 76/104頁
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9547 Mask Change 20/Oct/2010
標準包裝: 750
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
Data Sheet
AD9547
Rev. E | Page 73 of 104
DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B)
Table 58. Free-Running Frequency Tuning Word1
Address
Bit
Bit Name
Description
0x0300
[7:0]
Free-running frequency tuning word
(expressedas a 48-bit frequency
tuning word)
Free-running frequency tuning word, Bits[7:0].
0x0301
[7:0]
Free-running frequency tuning word, Bits[15:8].
0x0302
[7:0]
Free-running frequency tuning word, Bits[23:16].
0x0303
[7:0]
Free-running frequency tuning word, Bits[31:24].
0x0304
[7:0]
Free-running frequency tuning word, Bits[39:32].
0x0305
[7:0]
Free-running frequency tuning word, Bits[47:40].
1
The default free-running tuning word is 0x000000= 0, which equates to 0 Hz.
Table 59. Update TW
Address
Bit
Bit Name
Description
0x0306
[7:1]
Unused
Unused.
0
Update TW
A Logic 1 writtento this bit transfers the free-running frequency tuning word
(Register 0x0300 to Register 0x0305) to the register embeddedinthe tuning
word processinglogic. Note that it is not necessary to write the update TW bit
when the device is in free-run mode. This is an autoclearing bit.
Table 60. Pull-in RangeLower and Upper Limit1
Address
Bit
Bit Name
Description
0x0307
[7:0]
Pull-inrange lower limit (expressed
as a 24-bit frequency tuning word)
Lower limit pull-inrange, Bits[7:0].
0x0308
[7:0]
Lower limit pull-inrange, Bits[15:8].
0x0309
[7:0]
Lower limit pull-inrange, Bits[23:16].
0x030A
[7:0]
Pull-inrange upper limit (expressed
as a 24-bit frequency tuning word)
Upper limit pull-inrange, Bits[7:0].
0x030B
[7:0]
Upper limit pull-inrange, Bits[15:8].
0x030C
[7:0]
Upper limit pull-inrange, Bits[23:16].
1
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
Table 61. Open-Loop Phase Offset1
Address
Bit
Bit Name
Description
0x030D
[7:0]
Open-loop phase offset
(expressedinunitsofπ/215 radians)
DDS phase offset, Bits[7:0].
0x030E
[7:0]
DDS phase offset, Bits[15:8].
1
The default DDS phase offset is 0.
Table 62. Fixed Closed-Loop Phase Lock Offset1
Address
Bit
Bit Name
Description
0x030F
[7:0]
Fixedphase lock offset
(expressedin ps)
Fixedphase lock offset, Bits[7:0].
0x0310
[7:0]
Fixedphase lock offset, Bits[15:8].
0x0311
[7:0]
Fixedphase lock offset, Bits[23:16].
0x0312
[7:0]
Fixedphase lock offset, Bits[31:24].
0x0313
[7:0]
Fixedphase lock offset, Bits[39:32].
1
The default fixed closed loop phase lock offset is 0.
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