參數(shù)資料
型號(hào): AD9522-5BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 67/76頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9522-5
Rev. 0 | Page 7 of 76
CLOCK INPUTS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
01
2.4
GHz
High frequency distribution (VCO divider)
1.6
GHz
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider
Input Sensitivity, Differential
150
mV p-p
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns
Input Level, Differential
2
V p-p
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Input Common-Mode Voltage, VCM
1.3
1.57
1.8
V
Self-biased; enables ac coupling
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9
4.7
5.7
Self-biased
Input Capacitance
2
pF
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS CLOCK OUTPUTS
Termination = 100 Ω across differential pair
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,
OUT6, OUT7, OUT8, OUT9, OUT10, OUT11
Differential (OUT, OUT)
Output Frequency
800
MHz
The AD9522 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification
Output Differential Voltage, VOD
247
360
454
mV
VOH VOL measurement across a differential pair
at the default amplitude setting with output
driver not toggling; see Figure 17 for variation
over frequency
Delta VOD
25
mV
This is the absolute value of the difference
between VOD when the normal output is high vs.
when the complementary output is high
Output Offset Voltage, VOS
1.125
1.25
1.375
V
(VOH + VOL)/2 across a differential pair at the default
amplitude setting with output driver not toggling
Delta VOS
25
mV
This is the absolute value of the difference
between VOS when the normal output is high vs.
when the complementary output is high
Short-Circuit Current, ISA, ISB
14
24
mA
Output shorted to GND
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B, OUT2A,
OUT2B, OUT3A, OUT3B, OUT4A, OUT4B,
OUT5A, OUT5B, OUT6A, OUT6B, OUT7A,
OUT7B, OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A, OUT11B
Single-ended; termination = 10 pF
Output Frequency
250
MHz
Output Voltage High, VOH
VS 0.1
V
@ 1 mA load
Output Voltage Low, VOL
0.1
V
@ 1 mA load
Output Voltage High, VOH
2.7
V
@ 10 mA load
Output Voltage Low, VOL
0.5
V
@ 10 mA load
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