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參數資料
型號： AD9522-5BCPZ
廠商： Analog Devices Inc
文件頁數： 35/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.4GHZ 64LFCSP
標準包裝： 1
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS
電路數： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9522-5
Rev. 0 | Page 40 of 76
Table 30. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is X%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Even
Channel
divider
bypassed
50%
Odd = 3
Channel
divider
bypassed
33.3%
(1 + X%)/3
Odd = 5
Channel
divider
bypassed
40%
(2 + X%)/5
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Even
Odd
(N + 1)/
(N + M + 2)
50%, requires M = N + 1
Odd = 3
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 3
Odd
(N + 1)/
(N + M + 2)
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
Odd = 5
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 5
Odd
(N + 1)/
(N + M + 2)
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 31. Channel Divider Output Duty Cycle When the
VCO Divider Is Enabled and Set to 1
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Note that the channel divider must be enabled when the VCO
divider = 1.
Table 32. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Channel
divider
bypassed
Same as input
duty cycle
Same as input duty
cycle
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 33).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
section).
Table 33. Setting Phase Offset and Division
Divider
Start
High (SH)
Phase
Offset (PO)
Low Cycles
M
High Cycles
N
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
3
0x19A[4]
0x19A[3:0]
0x199[7:4]
0x199[3:0]
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
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