參數(shù)資料
型號: AD9522-5BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 60/76頁
文件大小: 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標準包裝: 1
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9522-5
Rev. 0 | Page 63 of 76
Reg.
Addr
(Hex) Bit(s) Name
Description
[7]
[6]
[5] [4]
[3]
[2]
Level or
Dynamic
Signal
Signal at STATUS Pin
1
0
1
0
DYN
Unselected reference to PLL (not available when in
differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential
mode); active low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of CLK frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD (active low).
1
0
LVL
Holdover active (active low).
1
LVL
LD pin comparator output (active low).
017
[1:0]
Antibacklash
pulse width
[1]
[0]
Antibacklash Pulse Width (ns)
0
2.9 (default)
0
1
1.3
1
0
6.0
1
2.9
018
[7]
Enable CMOS
reference input
dc offset
Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.
[7] = 0; disable dc offset (default).
[7] = 1; enable dc offset.
018
[6:5]
Lock detect
counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
[6]
[5]
PFD Cycles to Determine Lock
0
5 (default)
0
1
16
1
0
64
1
255
018
[4]
Digital lock
detect window
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time,
the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock
threshold.
[4] = 0; high range (default).
[4] = 1; low range.
018
[3]
Disable digital
lock detect
Digital lock detect operation.
[3] = 0; normal lock detect operation (default).
[3] = 1; disable lock detect.
019
[7:6]
R, A, B counters
SYNC pin reset
[7]
[6]
Action
0
Do nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Do nothing on SYNC.
019
[5:3]
R path delay
R path delay, see Table 2 (default: 0x0).
019
[2:0]
N path delay
N path delay, see Table 2 (default: 0x0).
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