參數(shù)資料
型號(hào): AD9522-5BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 51/76頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9522-5
Rev. 0 | Page 55 of 76
REGISTER MAP
Register addresses that are not listed in Table 43 are not used, and writing to those registers has no effect. The user should avoid writing
values other than 0x00 to register addresses marked unused.
Table 43. Register Map Overview
Addr
(Hex)
Parameter
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Serial Port Configuration
000
Serial port config
(SPI mode)
SDO active
LSB first/
addr incr
Soft reset
(self-
clearing)
Unused
Soft reset
(self-
clearing)
LSB first/
addr incr
SDO active
00
Serial port config
(IC mode)
Unused
Soft reset
(self-
clearing)
Unused
Soft reset
(self-
clearing)
Unused
00
001
Unused
N/A
002
Reserved (read-only)
N/A
003
Reserved (read-only)
N/A
004
Readback
control
Unused
Readback
active regs
00
EEPROM ID
005
EEPROM
customer
version ID
EEPROM customer version ID (LSB)
00
006
EEPROM customer version ID (MSB)
00
007
to
00F
Unused
00
PLL
010
PFD charge
pump
PFD polarity
Charge pump current
Charge pump mode
PLL power-down
7D
011
R counter
14-bit R counter, Bits[7:0] (LSB)
01
012
Unused
14-bit R counter, Bits[13:8] (MSB)
00
013
A counter
Unused
6-bit A counter
00
014
B counter
13-bit B counter, Bits[7:0] (LSB)
03
015
Unused
13-bit B counter, Bits[12:8] (MSB)
00
016
PLL_CTRL_1
Set CP pin
to VCP/2
Reset
R counter
Reset
A and B
counters
Reset all
counters
B counter
bypass
Prescaler P
06
017
PLL_CTRL_2
STATUS pin control
Antibacklash pulse width
00
018
PLL_CTRL_3
Enable CMOS
reference input
dc offset
Lock detect counter
Digital
lock
detect
window
Disable
digital
lock detect
Unused
06
019
PLL_CTRL_4
R, A, B counters
SYNC pin reset
R path delay
N path delay
00
01A
PLL_CTRL_5
Enable STATUS
pin divider
Ref freq
monitor
threshold
LD pin control
00
01B
PLL_CTRL_6
Enable CLK
frequency
monitor
Enable
REF2
(REFIN)
frequency
monitor
Enable
REF1
(REFIN)
frequency
monitor
REFMON pin control
00
01C
PLL_CTRL_7
Disable
switchover
deglitch
Select
REF2
Use
REF_SEL
pin
Enable
automatic
reference
switchover
Stay on REF2
Enable
REF2
Enable
REF1
Enable
differential
reference
00
01D
PLL_CTRL_8
Enable
Status_EEPROM
at STATUS pin
Enable
XTAL
OSC
Enable
clock
doubler
Disable
PLL status
register
Enable LD
pin
comparator
Unused
Enable
external
holdover
Enable
holdover
80
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