參數(shù)資料
型號: AD9522-5BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 62/76頁
文件大小: 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9522-5
Rev. 0 | Page 65 of 76
Reg.
Addr
(Hex) Bit(s) Name
Description
[5]
[4]
[3]
[2]
[1]
[0]
Level or
Dynamic
Signal
Signal at LD Pin
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of CLK frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD; active low.
1
0
LVL
Holdover active (active low).
1
LVL
Not applicable, do not use.
01B
[7]
Enable CLK
frequency
monitor
Enables or disables the CLK frequency monitor.
[7] = 0; disable the CLK frequency monitor (default).
[7] = 1; enable the CLK frequency monitor.
01B
[6]
Enable REF2
(REFIN)
frequency
monitor
Enables or disables the REF2 frequency monitor.
[6] = 0; disable the REF2 (REFIN) frequency monitor (default).
[6] = 1; enable the REF2 (REFIN) frequency monitor.
01B
[5]
Enable REF1
(REFIN)
frequency
monitor
REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
[5] = 0; disable the REF1 (REFIN) frequency monitor (default).
[5] = 1; enable the REF1 (REFIN) frequency monitor.
01B
[4:0]
REFMON pin
control
Selects the signal that is connected to the REFMON pin.
[4]
[3]
[2]
[1]
[0]
Level or
Dynamic
Signal
Signal at REFMON Pin
0
LVL
Ground, dc (default).
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
1
0
DYN
REF2 clock (not applicable in differential mode).
0
1
DYN
Selected reference to PLL (differential reference when in differential
mode).
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active high.
0
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
0
1
LVL
Status REF1 frequency (active high).
0
1
0
LVL
Status REF2 frequency (active high).
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK).
0
1
0
1
LVL
Status of CLK frequency (active high).
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
0
1
LVL
DLD; active low.
0
1
0
LVL
Holdover active (active high).
0
1
LVL
LD pin comparator output (active high).
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
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