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參數(shù)資料
| 型號： | AD9522-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.4GHZ 64LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9522-5
Rev. 0 | Page 49 of 76
SPI MSB/LSB FIRST TRANSFERS
The default mode of the AD9522 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9522 to unidirectional mode (0x000[7] = 1 and
0x000[0] = 1). In unidirectional mode, the readback data
appears on the SDO pin.
The AD9522 instruction word and byte data can be MSB first
or LSB first. Any data written to 0x000 must be mirrored; the
upper four bits ([7:4]) must mirror the lower four bits ([3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for 0x000, which mirrors Bit 4 and Bit 3. This sets the long
instruction mode, which is the default and the only mode
supported.
A readback request reads the data that is in the serial control
port buffer area or the data that is in the active registers (see
Figure 50). Readback of the buffer or active registers is controlled
by 0x004[0].
The default for the AD9522 is MSB first.
The AD9522 uses Register Address 0x000 to Register Address 0xB03.
When LSB first is set by 0x000[1] and 0x000[6], it takes effect
immediately because it affects only the operation of the serial
control port and does not require that an update be executed.
SERIAL
CONTROL
PORT
BUF
F
E
R
RE
G
IS
T
E
RS
UPDATE
REGISTERS
WRITE REGISTER 0x232 = 0x01
TO UPDATE REGISTERS
ACT
IV
E
RE
G
IS
T
E
RS
SCLK/SCL
SDO
SDIO/SDA
CS
072
40
-03
7
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte
transfer cycle.
Figure 50. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9522
SPI INSTRUCTION WORD (16 BITS)
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. In a multibyte transfer cycle, the internal byte
address generator of the serial port increments for each byte.
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits
(W1:W0) indicate the length of the transfer in bytes. The final
13 bits are the address (A12:A0) at which to begin the read or
write operation, see
.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], see Table 37.
Table 37. Byte Transfer Count
W1
The AD9522 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x232 for
multibyte I/O operations.
W0
Bytes to Transfer
0
1
0
1
2
1
Streaming mode always terminates when it reaches 0x232. Note
that unused addresses are not skipped during multibyte I/O
operations.
Table 38. Streaming Mode (No Addresses Are Skipped)
Write Mode
0
3
1
Streaming mode
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. Only Bits[A9:A0] are needed to cover
the range of the 0x232 registers used by the AD9522. Bits[A12:A10]
must always be 0b. For multibyte transfers, this address is the
starting byte address. In MSB first mode, subsequent bytes
increment the address.
Address Direction
Stop Sequence
LSB first
Increment
0x230, 0x231, 0x232, stop
MSB first
Decrement
0x001, 0x000, 0x232, stop
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