參數(shù)資料
型號(hào): AD9522-5BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 3/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9522-5
Rev. 0 | Page 11 of 76
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 500 MHz; VCO DIV = 5; LVDS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
248
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
290
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CLK = 200 MHz; VCO DIV = 1; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
288
fs rms
Calculated from SNR of ADC method
(broadband jitter)
SERIAL CONTROL PORT—SPI MODE
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
μA
Input Logic 0 Current
110
μA
The minus sign indicates that current is flowing out of
the AD9522, which is due to the internal pull-up resistor
Input Capacitance
2
pF
SCLK (INPUT) IN SPI MODE
SCLK has an internal 30 kΩ pull-down resistor in SPI
mode, but not in I2C mode
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
μA
Input Logic 0 Current
1
μA
Input Capacitance
2
pF
SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
1
μA
Input Logic 0 Current
1
μA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
4
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
11
ns
CS to SCLK Setup and Hold, tS, tC
2
ns
CS Minimum Pulse Width High, tPWH
3
ns
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