參數(shù)資料
型號： AD9522-3/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 76/84頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-3 CLK GEN
設(shè)計資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-3
主要屬性： 12 LVDS/24 CMOS 輸出，2 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-3
Rev. 0 | Page 78 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
1E1
[3]
Power-down VCO clock interface Powers down the interface block between VCO and clock distribution.
[3] = 0; normal operation (default).
[3] = 1; power down.
1E1
[2]
Power-down VCO and CLK
Powers down both the CLK input and VCO.
[2] = 0; normal operation (default).
[2] = 1; power down.
1E1
[1]
Select VCO or CLK
Selects either the VCO or the CLK as the input to VCO divider.
[1] = 0; select external CLK as input to VCO divider (default).
[1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
This bit must be set to use the PLL with the internal VCO.
1E1
[0]
Bypass VCO divider
Bypasses or uses the VCO divider.
[0] = 0; use VCO divider (default).
[0] = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Table 56. System
Reg.
Addr
(Hex) Bit(s) Name
Description
230
[3]
Disable power-on SYNC
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.
[3] = 0; enable the antiruntpulse circuitry (default).
[3] = 1; disable the antiruntpulse circuitry.
230
[2]
Power-down SYNC
Powers down the SYNC function.
[2] = 0; normal operation of the SYNC function (default).
[2] = 1; power-down SYNC circuitry.
230
[1]
Power-down distribution reference
Powers down the reference for the distribution section.
[1] = 0; normal operation of the reference for the distribution section (default).
[1] = 1; powers down the reference for the distribution section.
230
[0]
Soft SYNC
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed; that is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
[0] = 0; same as SYNC high.
[0] = 1; same as SYNC low.
Table 57. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
Description
232
[0]
IO_UPDATE
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
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