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參數(shù)資料
| 型號： | AD9522-3/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 68/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9522-3 CLK GEN |
| 設(shè)計資源： | AD9522 Eval Board Schematic AD9522 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9522-3 |
| 主要屬性： | 12 LVDS/24 CMOS 輸出，2 GHz VCO |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
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AD9522-3
Rev. 0 | Page 70 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
018
[0]
VCO calibration
now
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The
sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]);
then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete
control over when the VCO calibration occurs relative to the programming of other registers that can impact
the calibration (default = 0). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO
calibration.
019
[7:6]
R, A, B counters
SYNC pin reset
[7]
[6]
Action
0
Do nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Do nothing on SYNC.
019
[5:3]
R path delay
R path delay, see Table 2 (default: 0x0).
019
[2:0]
N path delay
N path delay, see Table 2 (default: 0x0).
01A
[7]
Enable STATUS
pin divider
Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the
R and N dividers.
[7] = 0; divide-by-4 disabled on STATUS pin (default).
[7] = 1; divide-by-4 enabled on STATUS pin.
01A
[6]
Ref freq monitor
threshold
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter).
[6] = 0; frequency valid if frequency is above 1.02 MHz (default).
[6] = 1; frequency valid if frequency is above 6 kHz.
01A
[5:0]
LD pin
control
Selects the signal that is connected to the LD pin.
[5]
[4]
[3]
[2]
[1]
[0]
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock; low = unlock, default).
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
1
HIZ
Tristate (high-Z) LD pin.
0
1
0
CUR
Current source lock detect (110 μA when DLD is true).
0
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as for REFMON.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active high.
1
0
1
0
LVL
Status of unselected reference (not available in differential
mode); active high.
1
0
1
LVL
Status REF1 frequency (active high).
1
0
1
0
LVL
Status REF2 frequency (active high).
1
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency (active high).
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
DLD; active high.
1
0
1
0
LVL
Holdover active (active high).
1
0
1
LVL
N/A, do not use.
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
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