參數(shù)資料
型號(hào)： AD9522-3/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 73/84頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-3 CLK GEN
設(shè)計(jì)資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-3
主要屬性： 12 LVDS/24 CMOS 輸出，2 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-3
Rev. 0 | Page 75 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
0F6
[7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0F7
[7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0F8
[7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0F9
[7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0FA
[7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0FB
[7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0FC
[7]
CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.
[7]
CSDLD Signal
OUT7 Enable Status
0
Not affected by CSDLD signal (default).
1
0
Asynchronous power-down.
1
Asynchronously enable OUT7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).
0FC
[6]
CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[5]
CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[4]
CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[3]
CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[2]
CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[1]
CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[0]
CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[3]
CSDLD En
OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[2]
CSDLD En
OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[1]
CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[0]
CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 54. LVDS Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
Description
190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
190
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
191
[7]
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
191
[6]
Divider 0 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
191
[5]
Divider 0 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
191
[4]
Divider 0 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
191
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).
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