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參數(shù)資料
| 型號(hào)： | AD9522-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 74/84頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9522-2 CLK GEN |
| 設(shè)計(jì)資源： | AD9522 Eval Board Schematic AD9522 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9522-2 |
| 主要屬性： | 12 LVDS/24 CMOS 輸出，2.2 GHz VCO |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
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AD9522-2
Rev. 0 | Page 76 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
192
[2]
Channel 0 power-down
Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high
impedance power-down mode by setting this bit.)
192
[0]
Disable Divider 0 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
193
[7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
193
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
194
[7]
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
194
[6]
Divider 1 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
194
[5]
Divider 1 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
194
[4]
Divider 1 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
194
[3:0]
Divider 1 phase offset
Phase offset (default: 0x0).
195
[2]
Channel 1 power-down
Channel 1 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into the high
impedance power-down mode by setting this bit.)
195
[0]
Disable Divider 1 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
196
[7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
196
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
197
[7]
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
197
[6]
Divider 2 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
197
[5]
Divider 2 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
197
[4]
Divider 2 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
197
[3:0]
Divider 2 phase offset
Phase offset (default: 0x0).
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