參數(shù)資料
型號(hào)： AD9522-2/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/84頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-2 CLK GEN
設(shè)計(jì)資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-2
主要屬性： 12 LVDS/24 CMOS 輸出，2.2 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-2
Rev. 0 | Page 33 of 84
Phase-Locked Loop (PLL)
PROGRAMMABLE
N DELAY
REFIN
CLK
REF1
REF2
BUF
STATUS
R
DI
V
ID
E
R
CL
O
CK
DO
UBL
E
R
STATUS
P
RO
G
RAM
M
A
BL
E
R
DE
L
AY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
R
E
NCE
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
OPTIONAL
REFIN
0
72
21
-0
64
Figure 40. PLL Functional Block Diagram
The AD9522 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9522 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be used to
clean up jitter and phase noise on a noisy reference. The exact
choice of PLL parameters and loop dynamics is application specific.
The flexibility and depth of the AD9522 PLL allow the part to
be tailored to function in many different applications and signal
environments.
Configuration of the PLL
The AD9522 allows flexible configuration of the PLL,
accommodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
for the R divider, the N divider, the PFD polarity (only applicable to
external VCO/VCXO), the antibacklash pulse width, the charge
pump current, the selection of internal VCO or external VCO/
VCXO, and the loop bandwidth. These are managed through
programmable register settings (see Table 48 and Table 52) and
by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings, and the design of the external loop filter is crucial to
the proper operation of the PLL.
ADIsimCLK is a free program that can help with the design
and exploration of the capabilities and features of the AD9522,
including the design of the PLL loop filter. The AD9516 model
found in ADIsimCLK Version 1.2 can also be used for modeling
the AD9522 loop filter. It is available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and the N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the phase/frequency detector (PFD) parameter in Table 2.
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