- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16534 > AD9522-2/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9522-2 CLK GEN PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9522-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 54/84頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9522-2 CLK GEN |
| 設(shè)計(jì)資源： | AD9522 Eval Board Schematic AD9522 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9522-2 |
| 主要屬性： | 12 LVDS/24 CMOS 輸出，2.2 GHz VCO |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 板 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
AD9522-2
Rev. 0 | Page 58 of 84
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space on the AD9522
that allows the user to specify which groups of registers are
stored to the EEPROM during EEPROM programming. Normally,
this segment does not need to be programmed by the user. Instead,
the default power-up values for the EEPROM buffer segment
allow the user to store all of the AD9522 register values from
Register 0x000 to Register 0x231 to the EEPROM.
For example, if users want to load only the output driver settings
from the EEPROM without disturbing the PLL register settings
currently stored in the AD9522, they can alter the EEPROM buffer
segment to include only the registers that apply to the output
drivers and exclude the registers that apply to the PLL configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Each register
section definition group contains the starting address and
number of bytes to be written to the EEPROM.
If the AD9522 register map were continuous from Address 0x000
to Address 0x232, only one register section definition group
would consist of a starting address of 0x000 and a length of
563 bytes. However, this is not the case. The AD9522 register
map is noncontiguous, and the EEPROM is only 512 bytes long.
Therefore, the register section definition group tells the EEPROM
controller how the AD9522 register map is segmented.
There are three operational codes: IO_UPDATE, end-of-data,
and pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-data
operational code and that an IO_UPDATE operation code appear
at least once before the end-of-data op code.
Register Section Definition Group
The register section definition group is used to define a continuous
register section for the EEPROM profile. It consists of three bytes.
The first byte defines how many continuous register bytes are in
this group. If the user puts 0x000 in the first byte, it means there
is only one byte in this group. If the user puts 0x001, it means
there are two bytes in this group. The maximum number of
registers in one group is 128.
The next two bytes are the low byte and high byte of the
memory address (16-bit) of the first register in this group.
IO_UPDATE (Operational Code 0x80)
The EEPROM controller uses Operational Code 0x80 to generate
an IO_UPDATE signal to update the active control register
bank from the buffer register bank during the download process.
At a minimum, there should be at least one IO_UPDATE
operational code after the end of the final register section definition
group. This is needed is so that at least one IO_UPDATE occurs
after all of the AD9522 registers are loaded when the EEPROM
is read. If this operational code is absent during a write to the
EEPROM, the register values loaded from the EEPROM are not
transferred to the active register space, and these values do not
take effect after they are loaded from the EEPROM to the AD9522.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses Operational Code 0xFF to
terminate the data transfer process between EEPROM and the
control register during the upload and download process. The
last item appearing in the EEPROM buffer segment should be
either this operational code or the pseudo-end-of-data
operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9522 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If users
want to define more than seven register section definition
groups, the pseudo-end-of-data operational code (0xFE) can be
used. During the upload process, when the EEPROM controller
receives the pseudo-end-of-data operational code, it halts the
data transfer process, clears the REG2EEPROM bit, and enables
the AD9522 serial port. Users can then program the EEPROM
buffer segment again and reinitiate the data transfer process by
setting the REG2EEPROM bit (0xB03[0]) to 1 and the
IO_UPDATE bit (0x232[0]) to 1. The internal I2C master then
begins writing to the EEPROM starting from the EEPROM address
held from the last writing.
This sequence enables more discrete instructions to be written
to the EEPROM than would otherwise be possible due to the
limited size of the EEPROM buffer segment. It also permits the
user to write to the same register multiple times with a different
value each time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FCBP110LD1L03 | CABLE 10.5GBPS 3M LASERWIRE |
| MCP121T-240E/TT | IC SUPERVISOR 2.32V LOW SOT-23B |
| AD9522-1/PCBZ | BOARD EVAL FOR AD9522-1 CLK GEN |
| VE-J4H-EZ-S | CONVERTER MOD DC/DC 52V 25W |
| ADCLK914/PCBZ | BOARD EVAL FOR ADCLK914 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9522-3 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
| AD9522-3/PCBZ | 功能描述:BOARD EVAL FOR AD9522-3 CLK GEN RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線(xiàn)路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線(xiàn)纜，CD 其它名稱(chēng):82EBV2081 |
| AD9522-3BCPZ | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND |
| AD9522-3BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9522-4 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。