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參數(shù)資料
| 型號： | AD9520-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 78/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9520-2 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-2 |
| 已供物品： | 板 |
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AD9520-2
Data Sheet
Rev. A | Page 8 of 80
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Source Current
Damage to the part can result if values are exceeded
Static
20
mA
Dynamic
16
mA
Sink Current
Damage to the part can result if values are exceeded
Static
8
mA
Dynamic
16
mA
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT RISE/FALL TIMES
Termination = 50 to VS_DRV 2 V
Output Rise Time, tRP
130
170
ps
20% to 80%, measured differentially (rise/fall times are
independent of VS and are valid for VS_DRV = 3.3 V and
2.5 V)
Output Fall Time, tFP
130
170
ps
80% to 20%, measured differentially (rise/fall times are
independent of VS and are valid for VS_DRV = 3.3 V and
2.5 V)
PROPAGATION DELAY, tPECL,
CLK-TO-LVPECL OUTPUT
For All Divide Values
850
1050
1280
ps
High frequency clock distribution configuration
800
970
1180
ps
Clock distribution configuration
Variation with Temperature
1.0
ps/°C
Termination = 50 to VS_DRV 2 V
LVPECL Outputs Sharing the
Same Divider
5
16
ps
VS_DRV = 3.3 V
5
20
ps
VS_DRV = 2.5 V
LVPECL Outputs on Different
Dividers
5
45
ps
VS_DRV = 3.3 V
5
60
ps
VS_DRV = 2.5 V
All LVPECL Outputs Across
Multiple Parts
190
ps
VS_DRV = 3.3 V and 2.5 V
CMOS OUTPUT RISE/FALL TIMES
Termination = open
Output Rise Time, tRC
750
960
ps
20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V
Output Fall Time, tFC
715
890
ps
80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V
Output Rise Time, tRC
965
1280
ps
20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V
Output Fall Time, tFC
890
1100
ps
80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V
PROPAGATION DELAY, tCMOS,
CLK-TO-CMOS OUTPUT
Clock distribution configuration
For All Divide Values
2.1
2.75
3.55
ns
VS_DRV = 3.3 V
3.35
ns
VS_DRV = 2.5 V
Variation with Temperature
2
ps/°C
VS_DRV = 3.3 V and 2.5 V
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs Sharing the Same
Divider
7
85
ps
VS_DRV = 3.3 V
10
105
ps
VS_DRV = 2.5 V
All CMOS Outputs on Different
Dividers
10
240
ps
VS_DRV = 3.3 V
10
285
ps
VS_DRV = 2.5 V
All CMOS Outputs Across
Multiple Parts
600
ps
VS_DRV = 3.3 V
620
ps
VS_DRV = 2.5 V
OUTPUT SKEW, LVPECL-TO-CMOS
OUTPUTS1
All settings identical; different logic type
Outputs Sharing the Same Divider
1.18
1.76
2.48
ns
LVPECL to CMOS on same part
Outputs on Different Dividers
1.20
1.78
2.50
ns
LVPECL to CMOS on same part
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
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