參數(shù)資料
型號(hào)： AD9520-2/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD9520-2
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9520-2
已供物品： 板
AD9520-2
Data Sheet
Rev. A | Page 40 of 80
A flowchart of the automatic/internal holdover function
operation is shown in Figure 47.
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
YES
07215-
069
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK, AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
REG 0x01D[3]: LD PIN COMPARATOR ENABLE.
0b = DISABLE; 1b = ENABLE. WHEN DISABLED,
THE HOLDOVER FUNCTION ALWAYS SENSES
THE LD PIN AS HIGH.
CHARGE PUMP IS MADE HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH IMPEDANCE
UNTIL THE REFERENCE RETURNS.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
Figure 47. Flowchart of Automatic/Internal Holdover Mode
The following registers affect the automatic/internal holdover
function:
Register 0x018[6:5]—lock detect counter. This changes
how many consecutive PFD cycles with edges inside the
lock detect window are required for the DLD indicator to
indicate lock. This impacts the time required before the LD
pin can begin to charge as well as the delay from the end of
a holdover event until the holdover function can be reengaged.
Register 0x018[3]—disable digital lock detect. This bit must
be set to 0b to enable the DLD circuit. Automatic/internal
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0]—lock detect pin control. Set these bits
to 000100b to program the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x01D[3]—LD pin comparator enable. 1b = enable;
0b = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1]—external holdover control.
Register 0x01D[0]—holdover enable. If holdover is
disabled, both external- and automatic/ internal holdover
are disabled.
In the following example, automatic holdover is configured with
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; digital lock detect window = high
range.
Register 0x018[3] = 1b; disable DLD normal operation.
Register 0x01A[5:0] = 000100b; program LD pin control to
current source lock detect mode.
Register 0x01C[4] = 1b; enable automatic switchover.
Register 0x01C[3] = 0b; prefer REF1.
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[1] = 0b; disable external holdover mode and
use automatic/internal holdover mode.
Register 0x01D[0] = 1b; enable holdover.
相關(guān)PDF資料
PDF描述
AD9516-5/PCBZ BOARD EVAL FOR AD9516-5 2.5GHZ
FCBP110LD1L05 CABLE 10.5GBPS 5M LASERWIRE
VE-JTV-EZ-S CONVERTER MOD DC/DC 5.8V 25W
AD9522-2/PCBZ BOARD EVAL FOR AD9522-2 CLK GEN
FCBP110LD1L03 CABLE 10.5GBPS 3M LASERWIRE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9520-3 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO
AD9520-3/PCBZ 功能描述:BOARD EVAL AD9520-3 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9520-3BCPZ 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
AD9520-3BCPZ-REEL7 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-4 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*