參數(shù)資料
型號(hào)： AD9520-2/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 65/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD9520-2
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9520-2
已供物品： 板
AD9520-2
Data Sheet
Rev. A | Page 68 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
[5:0]
LD pin control
Selects the signal that is connected to the LD pin.
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock; low = unlock, default).
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
1
HIZ
Tristate (high-Z) LD pin.
0
1
0
CUR
Current source lock detect (110 A when DLD is true).
0
X
LVL
Ground (dc). Used for all settings of these bits that are not otherwise specified in this table.
The selections that follow are also used for REFMON and STATUS pin control.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
1
0
1
LVL
Status of REF1 frequency; active high.
1
0
1
0
LVL
Status of REF2 frequency; active high.
1
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency; active high.
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
DLD; active high.
1
0
1
0
LVL
Holdover active; active high.
1
0
1
LVL
N/A. Do not use.
1
0
LVL
VS (PLL power supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency; active low.
1
0
LVL
Status of REF2 frequency; active low.
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency; active low.
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD; active low.
1
0
LVL
Holdover active; active low.
1
LVL
N/A. Do not use.
0x01B 7
Enable VCO
frequency
monitor
Enables or disables the VCO frequency monitor.
0: disables the VCO frequency monitor (default).
1: enables the VCO frequency monitor.
6
Enable REF2
(REFIN) frequency
monitor
Enables or disables the REF2 frequency monitor.
0: disables the REF2 frequency monitor (default).
1: enables the REF2 frequency monitor.
5
Enable REF1
(REFIN)
frequency
monitor
REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables the REF1 (REFIN) frequency monitor (default).
1: enables the REF1 (REFIN) frequency monitor.
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