參數(shù)資料
型號(hào)： AD9520-2/PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 23/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD9520-2
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9520-2
已供物品： 板
Data Sheet
AD9520-2
Rev. A | Page 3 of 80
REVISION HISTORY
8/13—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
General Description Section............................................................1
Changes to Table 2 ............................................................................4
Changes to Input Frequency Parameter; Change to Input
Sensitivity, Differential Parameter Test Conditions/Comments,
Table 3.................................................................................................7
Change to Output Differential Voltage, VOD Parameter Test
Conditions/Comments; Added Source Current and Sink
Current Parameters, Table 4 ............................................................7
Reordered Figure 2 to Figure 4........................................................9
Change to Reset Timing, Pulse Width Low Parameter, Table 15...15
Change to PLL Locked; One LVPECL Output Enabled
Parameter, fOUT Value in Test Conditions/Comments, Table 18..16
Change to Junction Temperature, Table 19; Reformatted
Table 19.............................................................................................17
Change to Pin 4, Pin 10, and Pin 22 Descriptions, Table 21 .....18
Deleted Figure 13, Renumbered Sequentially; Change to
fVCO Value in Caption, Figure 13 and Figure 14...........................22
Reordered Figure 31 and Figure 32; Moved Figure 34 and
Figure 35 to PLL External Loop Filter Section, Page 35;
Added Figure 33, Renumbered Sequentially...............................25
Change to Mode 0—Internal VCO and Clock Distribution
Section ..............................................................................................28
Change to Configuration of the PLL Section; Changes to
Charge Pump (CP) Section............................................................34
Changes to On-Chip VCO Section and PLL External Loop
Filter Section; Added Figure 40; Moved Figure 41 and Figure 42
from Typical Performance Characteristics Section to PLL
External Loop Filter Section; Changes to PLL Reference
Inputs Section ..................................................................................35
Changes to Reference Switchover Section ...................................36
Change to Prescaler Section and A and B Counters Section,
Changes to Table 29 ........................................................................37
Changes to Current Source Digital Lock Detect (CSDLD)
Section ..............................................................................................38
Changes to Frequency Status Monitors Section and VCO
Calibration Section .........................................................................41
Added Table 31, Renumbered Sequentially; Change to
Internal Zero Delay Mode Section ...............................................42
Change to Clock Frequency Division Section; Added
Channel Divider Maximum Frequency Section.........................45
Reformatted Table 36 to Table 39..................................................46
Change to Phase Offset or Coarse Time Delay Section.............47
Change to LVPECL Output Drivers Section; Changes to
CMOS Output Drivers Section .....................................................49
Changes to Soft Reset via the Serial Port Section and Soft
Reset to Settings in EEPROM When EEPROM Pin = 0b
via the Serial Port Section ..............................................................50
Change to Pin Descriptions Section and SPI Mode Operation
Section ..............................................................................................54
Changes to SPI Instruction Word (16 Bits) Section ...................55
Change to EEPROM Operations Section, Writing to the
EEPROM Section, and Reading from the EEPROM Section ...58
Changes to Programming the EEPROM Buffer Segment
Section and Register Section Definition Group Section;
Added Operational Codes Section Heading ...............................59
Changes to Table 50 ........................................................................61
Added Unused Bits to Register Map Descriptions Section;
Changes to Address 0x000, Bit 5, and Added Address 0x003,
Table 51; Changes to Address 0x000, Bit 5, and Added
Address 0x003, Table 52.................................................................64
Changes to Address 0x017, Table 54 ............................................66
Changes to Address 0x018, Bit 4 and Bits[2:1], Table 54...........67
Change to Address 0x01B, Bits[4:0], Table 54.............................69
Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,
Table 56.............................................................................................72
Changes to Address 0x197, Bit 5, Table 56 ..................................73
Changes to Address 0x19A, Bit 5, Table 56 .................................74
Changes to Table 60 ........................................................................75
Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,
Table 61.............................................................................................76
Change to Frequency Planning Using the AD9520 Section .....77
Added LVPECL Y-Termination and Far-End Thevenin
Termination Headings; Change to CMOS Clock Distribution
Section ..............................................................................................78
9/08—Revision 0: Initial Version
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