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| 型號(hào)： | AD9520-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9520-2 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-2 |
| 已供物品： | 板 |
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AD9520-2
Data Sheet
Rev. A | Page 34 of 80
Phase-Locked Loop (PLL)
PROGRAMMABLE
N DELAY
REFIN
CLK
REF1
REF2
BUF
STATUS
R
DI
V
IDE
R
CL
O
CK
DO
UB
L
E
R
STATUS
P
RO
G
RAM
M
ABL
E
R
DE
L
A
Y
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
RE
F
E
RE
NCE
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
VS_DRV
OPTIONAL
REFIN
0
7
215-
06
4
Figure 38. PLL Functional Block Diagram
The AD9520 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9520 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be used to
clean up jitter and phase noise on a noisy reference. The exact
choice of PLL parameters and loop dynamics is application specific.
The flexibility and depth of the AD9520 PLL allow the part to
be tailored to function in many different applications and signal
environments.
Configuration of the PLL
The AD9520 allows flexible configuration of the PLL, which
accommodates various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
for the R divider, N divider, PFD polarity (applicable only to the
external VCO/VCXO), antibacklash pulse width, charge pump
current, selection of internal VCO or external VCO/ VCXO, and
the loop bandwidth. These are managed through programmable
register settings (see Table 50 and Table 54) and by the design of
the external loop filter. Successful PLL operation and satisfactory
PLL loop performance are highly dependent upon proper
configuration of the PLL settings, and the design of the external
loop filter is crucial to the proper operation of the PLL.
ADIsimCLK is a free program that can help with the design
and exploration of the capabilities and features of the AD9520,
including the design of the PLL loop filter.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and the N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the phase/frequency detector (PFD) parameter in Table 2.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the
tuning pin of an external VCO) to move the VCO frequency up
or down. The CP can be set (Register 0x010[3:2]) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), or for pump-up or pump-down
(test modes). The CP current is programmable in eight steps from
(nominally) 0.6 mA to 4.8 mA. The CP current LSB is set by the
CPRSET resistor, which is nominally 5.1 kΩ. The exact value of
the CP current can be calculated with the following equation:
ICP (A) =
)
(
06
.
3
RSET
CP
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