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| 型號(hào)： | AD9520-2/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9520-2 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-2 |
| 已供物品： | 板 |
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AD9520-2
Data Sheet
Rev. A | Page 78 of 80
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 54 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 71) or Y-termination (see Figure 72) is recommended.
In both cases, VS of the receiving buffer should match VS_DRV. If it
does not, ac coupling is recommended (see Figure 73).
VS_DRV
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
07215-
045
Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV
LVPECL
Z0 = 50
VS = VS_DRV
LVPECL
50
Z0 = 50
07215-
047
Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination
VS_DRV
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
07215-
046
Figure 73. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-Termination
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
where VS_DRV = 2.5 V, the 50 termination resistor connected to
ground in Figure 72 should be changed to 19 .
Far-End Thevenin Termination
Far-end Thevenin termination uses a resistor network to provide
50 termination to a dc voltage that is below VOL of the LVPECL
receiving buffer. Although the resistor combination shown results
in a dc bias point of VS_DRV 2 V, the actual common-mode voltage
is VS_DRV 1.3 V because there is additional current flowing
from the AD9520 LVPECL driver through the pull-down resistor.
The circuit is identical for the case where VS_DRV = 2.5 V, except that
the pull-down resistor is 62.5 and the pull-up resistor is 250 .
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually turned
on or off and set as inverting or noninverting. These outputs are
3.3 V or 2.5 V CMOS compatible. However, every output driver
(including the LVPECL drivers) must be run at either 2.5 V or
3.3 V. The user cannot mix and match 2.5 V and 3.3 V outputs.
When using single-ended CMOS clocking, consider the following
guidelines:
Using the CMOS drivers in the same output channel group
as the LVPECL drivers may result in performance degradation
of the LVPECL drivers. Where possible, program the two
CMOS drivers that form the same output of a differential
pair to be out of phase such that one driver is high while
the other is low. It is recommended that the evaluation
board be used to verify the performance of the AD9520 in
demanding applications where both CMOS and LVPECL
drivers are in the same group, and the very best jitter
performance is required.
If possible, design point-to-point connections such that
each driver has only one receiver. Connecting outputs in
this manner allows for simple termination schemes and
minimizes ringing due to possible mismatched impedances
on the output trace. Series termination at the source is
generally required to provide transmission line matching
and/or to reduce current transients at the driver.
The value of the resistor is dependent on the board design
and timing requirements (typically 10 to 100 is used).
CMOS outputs are also limited in terms of the capacitive
load or trace length that they can drive. Typically, trace
lengths of less than 3 inches are recommended to preserve
signal rise/fall times and signal integrity.
CMOS
10
60.4
(1.0 INCH)
MICROSTRIP
07215-
076
Figure 74. Series Termination of CMOS Output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
| AD9520-3/PCBZ | 功能描述:BOARD EVAL AD9520-3 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-3BCPZ | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9520-3BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
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