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參數(shù)資料
| 型號(hào)： | AD9518-2A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9518-2A |
| 設(shè)計(jì)資源： | AD9518 Schematics AD9518 Gerber Files AD9518-2 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9518-2A |
| 主要屬性： | 2 輸入，6 輸出，2.2GHz VCO |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
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AD9518-2
Data Sheet
Rev. C | Page 26 of 64
Phase-Locked Loop (PLL)
CLK
CHARGE PUMP
R DIVIDER
CP
VCP
VSGND
STATUS
CPRSET
DIST
REF
RSET
DIVIDE BY
2, 3, 4, 5, OR 6
A/B
COUNTERS
LD
N DIVIDER
REFMON
LF
BYPASS
LOW DROPOUT
REGULATOR (LDO)
0
1
0
1
VCO
P, P + 1
PRESCALER
REF2
REF1
REFERENCE
SWITCHOVER
HOLD
VCO STATUS
REF_SEL
LOCK
DETECT
STATUS
CLK
PHASE
FREQUENCY
DETECTOR
PROGRAMMABLE
N DELAY
PROGRAMMABLE
R DELAY
PLL
REF
REFIN (REF1)
REFIN (REF2)
06
43
1-
0
64
Figure 31. PLL Functional Blocks
The AD9518 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop, or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9518 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited
to clean up jitter and phase noise on a noisy reference. The exact
choices of PLL parameters and loop dynamics are very application
specific. The flexibility and depth of the AD9518 PLL allow the
part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9518 allows flexible configuration of the PLL,
accommodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse width,
the charge pump current, the selection of internal VCO or
external VCO/VCXO, and the loop bandwidth. These are
managed through programmable register settings (see Table 42
and Table 44) and by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings. The design of the external loop filter is crucial to the
proper operation of the PLL. A thorough knowledge of PLL
theory and design is helpful.
ADIsimCLK (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9518, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which in turn determines the correct
antibacklash pulse setting. The antibacklash pulse setting is
specified in the phase/frequency detector parameter of Table 2.
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