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參數(shù)資料
| 型號： | AD9148BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QD 1GSPS 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | TxDAC+® |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 2.22W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電流，單極 |
| 采樣率（每秒）： | 1G |
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Data Sheet
AD9148
Rev. B | Page 55 of 72
When using the fine modulator, the maximum signal bandwidth of
0.8 × fDATA is always achieved.
Updating the Frequency Tuning Word
The frequency tuning word registers are not updated immediately
upon writing as the other configuration registers do. After loading
the FTW registers with the desired values, Bit 2 of Register 0x5A
must transition from 0 to 1 for the new FTW to take effect.
Phase Offset Adjustment
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9148s
are programmed for synchronization. The phase offset allows
for the adjustment of the output timing between the devices.
The static phase adjustment is sourced from the NCO Phase
Offset[15:0] value located in Register 0x58 and Register 0x59.
QUADRATURE PHASE CORRECTION
The purpose of the quadrature phase correction block is to
enable compensation of the phase imbalance of the analog
quadrature modulator following the DAC. If the quadrature
modulator has a phase imbalance, the unwanted sideband
appears with significant energy. Tuning the quadrature
phase adjust value can optimize image rejection in single
sideband radios.
Ordinarily, the I and Q channels have an angle of precisely 90°
between them. The quadrature phase adjustment is used to
change the angle between the I and Q channels. When I Phase
Adj, Bits[9:0] (Register 0x28 and Register 0x29), are set to
1000000000b, the I DAC output moves approximately 1.75°
away from the Q DAC output, creating an angle of 91.75°
between the channels. When I Phase Adj, Bits[9:0] (Register 0x28
and Register 0x29), are set to 0111111111b, the I DAC output
moves approximately 1.75° toward the Q DAC output, creating
an angle of 88.25° between the channels.
Q Phase Adj, Bits[9:0] (Register 2A and Register 2B), work in a
similar fashion. When Q Phase Adj, Bits[9:0] (Register 2A and
Register 2B), are set to 1000000000b, the Q DAC output moves
approximately 1.75° away from the I DAC output, creating an
angle of 91.75° between the channels. When Q Phase Adj[9:0]
is set to 0111111111b, the Q DAC output moves approximately
1.75° toward the I DAC output, creating an angle of 88.25°
between the channels.
Based on these two endpoints, the combined resolution of
the phase compensation register is approximately 3.5°/1024 or
0.00342° per code. When both I Phase Adj, Bits[9:0] (Register 0x28
and Register 0x29), and Q Phase Adj, Bits[9:0] (Register 2A and
Register 2B), are used, the full phase adjustment range is ±3.5°.
DC OFFSET CORRECTION
The dc value of the I data path and the Q data path can be
independently controlled by adjusting I DC Offset, Bits[15:0],
and Q DC Offset, Bits[15:0], values in Register 0x2C through
Register 0x2F. These values are added directly to the data path
values. Care should be taken not to overrange the transmitted
values.
Figure 72 shows how the DAC offset current varies as a function of
I DC Offset, Bits[15:0], and Q DC Offset, Bits[15:0], values. With
the digital inputs fixed at midscale (0x000, twos complement
currents as the DC offset value is swept from 0 to 65,535.
Because IOUTxP and IOUTxN are complementary current outputs,
the sum of IOUTxP and IOUTxN is always 20 mA.
0x0000
0x4000
0x8000
0xC000
0xFFFF
5
10
15
20
5
10
15
20
0
DAC OFFSET VALUE
I O
UT
x
N
(mA)
I O
UT
x
P
(
mA)
08910-
131
Figure 72. DAC Output Currents vs. DC Offset Value
DIGITAL GAIN CONTROL
The last block in each datapath is an 8-bit scalar (Register 0x50
and Register 0x51) that can be used for digital gain control. The
IGain Control, Bits[7:0] (Register 0x50), and QGain control,
Bits[7:0] (Register 0x51), values directly scale the samples written to
the IDAC and QDAC, respectively. The bit weighting is MSB = 21
and LSB = 2-6, which yields a multiplier range of 0 to 3.984375.
The scale factor for each data path is calculated as
64
]
0
:
7
[
64
]
0
:
7
[
QGain
or
IGain
r
ScaleFacto =
Take care not to overrange the DAC when using a scale factor
greater than 1.
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| AD9148BBPZ | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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