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| 型號(hào)： | AD9148BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QD 1GSPS 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 2.22W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9148
Data Sheet
Rev. B | Page 42 of 72
FIFO OPERATION
DAC1
AND
DAC2
32
32 BITS
÷INT
DCIA
DCIB
DACCLK
DATA
PORT A
DATA
PORT B
DATA
PATHS
DATA
ASSEMBLER
INPUT
LATCH
DATA
ASSEMBLER
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
32
DAC3
AND
DAC4
32
DATA
PATHS
32
WRITE PTR
RESET
WRITE PTR
RESET
READ
PTR
RESET
SYNC
LOGIC
FIFO RATE/
DATA RATE
FI
F
O
A
O
F
S
[2:
0]
FI
F
O
B
OF
S
[2
:0
]
32 BITS
FRAMEB
FRAMEA
LOGIC
RE
AD
P
O
IN
T
E
R
A
R
E
AD
P
O
INT
E
R
B
32
INTERFACE
MODE
ONE
DCI
WRITE PTR B
WRITE PTR A
08
91
0-
049
Figure 50. Block Diagram of FIFO
The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one
per dual DAC) designed to relax the timing relationship between
the data arriving at the DAC input ports and the internal DAC
data rate clock. The FIFOs can also be used to provide an adjustable
pipeline delay between the DCIx clocks and the DACCLK allowing
realignment of data input in a multichip system. This significantly
increases the timing budget of the interface.
Figure 50 shows the block diagram of the datapath through the
FIFO. The data is latched into the device, is formatted, and is then
written into the FIFO register determined by the FIFO write
pointer. The value of the write pointer is incremented every time a
new word is loaded into the FIFO. Meanwhile, data is read from
the FIFO register determined by the read pointer and fed into
the digital datapath. The value of the read pointer is updated
every time data is read into the datapath from the FIFO. This
happens at the data rate, that is, the DACCLK rate divided by
the interpolation ratio. The difference between the write and
read pointers represents the FIFO pipeline delay and is
important to take into account when understanding the overall
pipeline delay of the AD9148.
In single-port and byte interface modes, the incoming digital data is
sampled at twice the data rate (DCIA). The data is then assembled
based on the interface mode. At the output of the data assembler
block, the data samples for DAC 1 and DAC 2 are written to FIFO A
and the data samples for DAC 3 and DAC 4 are written to FIFO B
at the data rate.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO is the same as the write pointer and the
read pointer being equal. When both pointers are equal, an attempt
is made to read and write a single FIFO register simultaneously.
This simultaneous register access leads to unreliable data transfer
through the FIFO and must be avoided.
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| AD9148BBPZ | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9148BBPZRL | 功能描述:IC DAC 16BIT SPI/SRL 196BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9148BPCZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148BPCZRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
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