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| 型號(hào)： | AD7471 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.4us，642μW Micropower12-Bit Parallel ADC(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器) |
| 中文描述： | 1.4us，642μWMicropower12位并行ADC（12位高速，低耗，逐次逼近式的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 203K |
| 代理商： | AD7471 |
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AD7471
–9–
REV. PrB
Prelimnary Technical Data
PRELMNARY
DATA
78
5.8mA
TECHNCAL
C U R R E N T
C ON SU M PT ION
A D C T R A NSF E R F UNC T ION
T he output coding of the AD7471 is straight binary. T he
designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, etc.). T he LSB size is =
(REF IN)/4096. T he ideal transfer characteristic for the
AD7471 is shown in Figure 6.
phase. R3 represents the source impedance of a buffer
amplifier or resistive network, R1 is an internal switch
resistance, R2 is for bandwidth control and C1 is the sam-
pling capacitor. C2 is back-plate capacitance and switch
parasitic capacitance.
During the acquisition phase the sampling capacitor must
be charged to within 1 LSB of its final value.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
A
0V 1/2L SB
+ V
R E F
-1L SB
AN AL OG IN PU T
1L SB = V
R E F
/4096
Figure 6. Transfer Characteristic for 12 Bits
A C A C QUISIT ION T IME
In ac applications it is recommended to always buffer ana-
log input signals. T he source impedance of the drive cir-
cuitry must be kept as low as possible to minimize the
acquisition time of the ADC. Large values of impedance
at the VIN pin of the ADC will cause the T HD to de-
grade at high input frequencies.
T Y PIC A L A M PL IF IE R
IN PU T
BU F F E R S
SN R
50kH z
T H D
50kH z
A D 8047
70
A D 8051
68.6
78
4.4mA
A D 7471
D Y N A M IC
PE R F OR M A N C E
SPE C IF IC A T ION S
Figure 7. Recommended Input Buffers
R eference Input
T he following references are best suited for use with the
AD 7471.
AD R 291
AD 780
AD 192
For optimum performance, a 2.5 V reference is recom-
mended. T he part can function with a reference up to 3 V
and down to 2 V, but the performance deteriorates.
D C Acquisition T ime
T he ADC starts a new acquisition phase at the end of a
conversion and ends it on the falling edge of the
CONVST
signal. At the end of conversion there is a set-
tling time associated with the sampling circuit. T his set-
tling time lasts approximately 250 ns. T he analog signal
on V
IN
is also being acquired during this settling time;
therefore, the minimum acquisition time needed is ap-
proximately 250 ns.
Figure 8 shows the equivalent charging circuit for the
sampling capacitor when the ADC is in its acquisition
R 3
R 1
125
V
V
IN
C 1
22pF
C 2
8pF
R 2
636
V
Figure 8. Equivalent Sampling Circuit
A NA L OG INPUT
Figure 9 shows the equivalent circuit of the analog input
structure of the AD7471. T he two diodes, D1 and D2,
provide ESD protection for the analog inputs. T he capaci-
tor C3 is typically about 4 pF and can be primarily attrib-
uted to pin capacitance. T he resistor R1 is an internal
switch resistance. T his resistor is typically about 125r.
T he capacitor C1 is the sampling capacitor while R2 is
R 1
125
V
V
IN
C 1
22pF
C 2
8pF
R 2
636
V
D 1
D 2
C 3
4pF
V
D D
Figure 9. Equivalent Analog Input Circuit
C L OC K SOUR C E S
T he max CLK specification for the AD7471 is 10 MHz.
T his frequency is a standard off-the-shelf oscillator fre-
quency. Many manufacturers produce oscillator modules
at this frequency or close to this frequency. Of course any
clock source can be used, not just crystal oscillators.
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