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| 型號： | AD7471 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.4us，642μW Micropower12-Bit Parallel ADC(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器) |
| 中文描述： | 1.4us，642μWMicropower12位并行ADC（12位高速，低耗，逐次逼近式的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 203K |
| 代理商： | AD7471 |
AD7471
–6–
REV. PrB
Prelimnary Technical Data
Analog Supply Voltage, +2.7 V to +5.25 V. T his is the only supply voltage for all analog circuitry on
the AD7471. T he AV
DD
and DV
DD
voltages should ideally be at the same potential and must not be more
than 0.3 V apart even on a transient basis. T his supply should be decoupled to AGND.
Digital Supply Voltage, +2.7 V to +5.25 V. T his is the supply voltage for all digital circuitry on the
AD7471 apart from the output drivers. T he DV
DD
and AV
DD
voltages should ideally be at the same po-
tential and must not be more than 0.3 V apart even on a transient basis. T his supply should be de-
coupled to DGND.
Analog Ground. Ground reference point for all analog circuitry on the AD7471. All analog input sig-
nals and any external reference signal should be referred to this AGND voltage. T he AGND and
DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even on
a transient basis.
Digital Ground. T his is the ground reference point for all digital circuitry on the AD7471. T he DGND
and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even
on a transient basis.
Analog Input. Single-ended analog input channel. T he input range is 0 V to REFIN. T he analog input
presents a high dc input impedance.
Supply Voltage for the Output Drivers, +2.7 V to +5.25 V. T his voltage determines the output high
voltage for the data output pins. It allows the AV
DD
and DV
DD
to operate at 5 V (and maximize the dy-
namic performance of the ADC) while the digital outputs can interface to 3 V logic.
Data Bit 0 to Data Bit 11. Parallel digital outputs that provide the conversion result for the part. T hese
are three-state outputs that are controlled by
CS
and
RD
. T he output high voltage level for these outputs
is determined by the V
DRIVE
input.
TECHNCAL
reference is 2.5 V ±1% for specified performance.
PIN F UNC T ION D E SC R IPT ION
Pin
Mnemonic
Function
CS
Chip Select. Active low logic input used in conjunction with
RD
to access the conversion result. T he
conversion result is placed on the data bus following the falling edge of both
CS
and
RD
.
CS
and
RD
are both connected to the same AND gate on the input so the signals are interchangeable.
CS
can be
hardwired permanently low.
Read Input. Logic Input used in conjunction with
CS
to access the conversion result. T he conversion
result is placed on the data bus following the falling edge of both
CS
and
RD
.
CS
and
RD
are both con-
nected to same AND gate on the input so the signals are interchangeable.
CS
and
RD
can be hardwired
permanently low in which case, the data bus is always active and the result of the new conversion is
clocked out slightly before to the BUSY line going low.
Conversion Start Input. Logic Input used to initiate conversion. T he input track/hold amplifier goes
from track mode to hold mode on the falling edge of
CONVST
and the conversion process is initiated
at this point. T he conversion input can be as narrow as 10 ns. If the
CONVST
input is kept low for the
duration of conversion and is still low at the end of conversion, the part will automatically enter sleep
mode. If the part enters this sleep mode, the next rising edge of
CONVST
wakes up the part. Wake-up
time for the part is typically 1 μs.
Master Clock Input. T he clock source for the conversion process is applied to this pin. Conversion time
for the AD7471 takes 14 clock cycles. T he frequency of this master clock input, therefore, determines
the conversion time and achievable throughput rate. While the ADC is not converting, the Clock-In pad
is in three-state and thus no clock is going through the part. T he frequency range for this clock input is
from 1K Hz to 10MHz.
BUSY Output. Logic Output indicating the status of the conversion process. T he BUSY signal goes
high after the falling edge of
CONVST
and stays high for the duration of conversion. Once conversion
is complete and the conversion result is in the output register, the BUSY line returns low. T he track/
hold returns to track mode just prior to the falling edge of BUSY and the acquisition time for the part
begins when BUSY goes low. If the
CONVST
input is still low when BUSY goes low, the part auto-
matically enters its sleep mode on the falling edge of BUSY.
Reference Input. An external reference must be applied to this input. T he voltage range for the external
RD
CONVST
C L K IN
BU SY
REF IN
AV
DD
DV
DD
A G N D
D G N D
V
IN
V
DRIVE
D B0–D B11
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