參數(shù)資料
型號: AD7471
廠商: Analog Devices, Inc.
英文描述: 1.4us,642μW Micropower12-Bit Parallel ADC(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器)
中文描述: 1.4us,642μWMicropower12位并行ADC(12位高速,低耗,逐次逼近式的A / D轉(zhuǎn)換器)
文件頁數(shù): 7/13頁
文件大?。?/td> 203K
代理商: AD7471
AD7471
–7–
REV. PrB
Prelimnary Technical Data
nonfundamental signals up to half the sampling frequency
(f
S
/2), excluding dc. T he ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. T he theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
Signal to
(
Noise + Distortion
)
=
(6.02
N +
1.76)
dB
T hus for a 12-bit converter, this is 74 dB and for a 10-bit
converter is 62 dB.
TECHNCAL
T E R M INO L O G Y
Integral Nonlinearity
T his is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
T he endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full
scale, a point 1/2 LSB above the last code transition.
D ifferential Nonlinearity
T his is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the
AD C .
Offset E rror
T his is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e., AGND + 1
L SB.
Gain E rror
T he last transition should occur at the analog value 1 1/2
LSB below the nominal full scale. T he first transition is a
1/2 LSB above the low end of the scale (zero in the case of
AD7471). T he gain error is the deviation of the actual
difference between the first and last code transitions from
the ideal difference between the first and last code transi-
tions with offset errors removed.
T rack/Hold Acquisition T ime
T he track/hold amplifier returns into track mode after the
end of conversion. T rack/Hold acquisition time is the time
required for the output of the track/hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
T his is the measured ratio of signal to (noise + distortion)
at the output of the A/D converter. T he signal is the rms
amplitude of the fundamental. Noise is the sum of all
T otal H armonic D istortion
T otal harmonic distortion (T HD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7471 it
is defined as:
THD (dB)
=
20 log
(V
22
+
V
32
+
V
42
+
V
52
+
V
62
)
V
1
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to f
S
/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation D istortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n is
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
T he AD7471 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. T he calculation of
the intermodulation distortion is as per the T HD specifi-
cation where it is the ratio of the rms sum of the indi-
vidual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
A perture D elay
In a sample/hold, the time required after the hold com-
mand for the switch to open fully is the aperture delay.
T he sample is, in effect, delayed by this interval, and the
hold command would have to be advanced by this amount
for precise timing.
A perture Jitter
Aperture jitter is the range of variation in the aperture
delay. In other words, it is the uncertainty about when the
sample is taken. Jitter is the result of noise which modu-
lates the phase of the hold command. T his specification
establishes the ultimate timing error, hence the maximum
sampling frequency for a given resolution. T his error will
increase as the input dV/dt increases.
相關(guān)PDF資料
PDF描述
AD7485 1 MSPS, Serial 14-Bit SAR ADC
AD7485BST 1 MSPS, Serial 14-Bit SAR ADC
AD75019JP 16 x 16 Crosspoint Switch Array
AD75019 Crosspoint Switch Array(16×16正交開關(guān)陣列)
AD7506KN ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7472 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD7470/AD7472: 1.75MSPS. 4mW 10-Bit/12-Bit SAR ADC Data Sheet (Rev. A. 3/00)
AD7472AR 功能描述:IC ADC 12BIT PARALLEL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率(每秒):3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散(最大):- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:-
AD7472AR-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 1.5Msps 12-bit Parallel 24-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 1.5MSPS PARALLEL ADC I.C. - Tape and Reel
AD7472AR-REEL7 功能描述:IC ADC 12BIT PARALLEL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率(每秒):300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散(最大):75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC(0.295",7.50mm 寬) 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端,單極;1 個單端,雙極
AD7472ARU 功能描述:IC ADC 12BIT PARALLEL 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率(每秒):300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散(最大):75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC(0.295",7.50mm 寬) 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端,單極;1 個單端,雙極