參數(shù)資料
型號(hào)： AD7471
廠商： Analog Devices, Inc.
英文描述： 1.4us，642μW Micropower12-Bit Parallel ADC(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器)
中文描述： 1.4us，642μWMicropower12位并行ADC（12位高速，低耗，逐次逼近式的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 4/13頁(yè)
文件大小： 203K
代理商： AD7471
AD7471
TIMNGSPECIFICATIONS
1
–4–
REV. PrB
Prelimnary Technical Data
PRELMNARY
TECHNCAL
Limit at T
MIN
, T
MAX
AD7471 Units
Parameter
f
CLK 2
Description
1
10
1.4
1
250
10
10
30
0
0
20
15
8
0
100
kHz min
MHz max
us max
us max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
t
CONVERT
t
WAKEUP
t
acq
t
1
t
23
t
CLK
= 1/f
CLK IN
Wakeup T ime
Acquisition T ime
CONVST
Pulse Width
CONVST
to BUSY Delay, V
DD
= 5 V
CONVST
to BUSY Delay, V
DD
= 3 V
BUSY to
CS
Setup T ime
RD
Pulse Width
Data Access T ime After Falling Edge of
RD
Bus Relinquish T ime After Rising Edge of
RD
CS
to
RD
Hold T ime
Quite T ime
t
3
t
44
t
5
t
64
t
75
t
8
t
9
NOT ES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 Volts. See
Figure 2.
2
Mark/Space ratio for the CLK input is 40/60 to 60/40.
3
t
2
is 35 ns max @ 125°C.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5
t
7
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
Specifications subject to change without notice.
(
V
DD
= +2.7 V to +5.25 V, REF IN= 2.5 V; T
A
= T
MN
to T
MAX
, unless otherwse noted.)
Figure 1. Load Circuit for Digital Output Timing
Specifications
+1.6V
IOL
200μA
200μA
IOH
TO
OUTPUT
PIN
CL
50pF
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