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| 型號： | AD7471 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.4us，642μW Micropower12-Bit Parallel ADC(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器) |
| 中文描述： | 1.4us，642μWMicropower12位并行ADC（12位高速，低耗，逐次逼近式的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 203K |
| 代理商： | AD7471 |
AD7471
–11–
REV. PrB
Prelimnary Technical Data
PRELMNARY
TECHNCAL
OP E R A T ING MOD E S
T he AD7471 has two possible modes of operation de-
pending on the state of the
CONVST
pulse at the end of a
conversion, Mode 1 and Mode 2. T here is a continuous
clock on the CLK IN pin.
Mode 1 (High Speed Sampling)
In this mode of operation the
CONVST
pulse is brought
high before the end of conversion i.e., before the BUSY
goes low (see Figure 10). If the
CONVST
pin is brought
from high to low while BUSY is high, the conversion is
restarted. When operating in this mode a new conversion
should not be initiated until 250 ns after BUSY goes low.
T his acquisition time allows the track/hold circuit to accu-
rately acquire the input signal. As mentioned earlier, a
read should not be done during a conversion. T his mode
facilitates the fastest throughput times for the AD7471.
Mode 2 (Sleep Mode)
Figure 13 shows AD7471 in Mode 2 operation where the
ADC goes into sleep mode after conversion. T he
CONVST
line is brought low to initiate a conversion and
remains low until after the end of conversion. If
CONVST
goes high and low again while BUSY is high,
the conversion is restarted. Once the BUSY line goes from
a high to a low, the
CONVST
line has its status checked
and, if low, the part enters sleep mode.
T he device wakes up again on the rising edge of the
CONVST
signal. T here is a wake-up time of typically 1
μs after the rising edge of
CONVST
before the BUSY
line can go high to indicate start of conversion. BUSY will
only go high once
CONVST
goes low. T he
CONVST
line
can go from a high to a low during this wake-up time, but
the conversion will still not be initiated until after the 1 μs
wake-up time. Superior power performance can be
achieved in this mode of operation by waking up the
AD7471 only to carry out a conversion.
Burst Mode
Burst mode on the AD7471 is a subsection of Mode 1
and Mode 2, the clock is noncontinuous. Figure 12 shows
how the ADC works in burst mode for Mode 2. T he clock
needs only to be switched on during conversion, maxi-
mum of 14 clock cycles for the AD7471. As the clock is
off during nonconverting intervals, system power is saved.
T he BUSY signal can be used to gate the CLK IN pulses.
T he ADC does not begin the conversion process until the
first CLK IN rising edge after BUSY goes high. T he
clock needs to start less than two clock cycles away from
the
CONVST
active edge otherwise INL deteriorates;
e.g., if the clock frequency is 10 MHz the clock must start
within 200 ns of
CONVST
going low. In Figure 12 the
A-D converter section is put into sleep mode once conver-
sion is completed and on the rising edge of
CONVST
it is
woken up again; the user must be wary of the wake-up
time as this will reduce the sampling rate of the ADC.
V
DRIVE
T he V
DRIVE
pin is used as the voltage supply to the output
drivers and is a separate supply from AV
DD
and DV
DD
. T he
purpose of using a separate supply for the output drivers is
that the user can vary the output high voltage, V
OH
, from
the V
DD
supply to the AD7471. For example, if AV
DD
and
DV
DD
is using a 5 V supply, the V
DRIVE
pin can be powered
from a 3 V supply. T he ADC has better dynamic perfor-
mance at 5 V than at 3 V, so operating the part at 5 V,
while still being able to interface to 3 V parts, pushes the
AD7471 to the top bracket of high performance 12-bit A/
Ds. Of course, the ADC can have its V
DRIVE
and DV
DD
pins
connected together and be powered from a 3 V or 5 V
supply.
All outputs are powered from V
DRIVE
. T hese are all the data
out pins and the BUSY pin. T he
CONVST
,
CS
,
RD
and
CLK IN signals are related to the DV
DD
voltage.
P O W E R - U P
It is recommended that the user performs a dummy con-
version after power-up, as the first conversion result could
be incorrect. T his also ensures that the parts is in the cor-
rect mode of operation. T he recommended power-up se-
quence is as follows:
1 > GND
4 > Digital Inputs
2 > V
DD
5 > REF IN
3 > V
DRIVE
6 > V
IN
CONVST
BU SY
CS
RD
D Bx
t
W A K E U P
t
C ON V E R T
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