參數(shù)資料
型號(hào)： AD1846JP
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 277K
代理商： AD1846JP
AD1846
REV. A
–23–
DMA T iming
Below, timing parameters are shown for 8-Bit Mono Sample
Read/Capture and Write/Playback DMA transfers in Figures 13
and 14. Note that in single-channel DMA mode, the Read/
Capture cycle timing shown in Figure 13 applies to the PDRQ
and
PDAK
signals, rather than the CDRQ and
CDAK
signals
as shown. T he same timing parameters apply to multibyte trans-
fers. T he relationship between timing signals is shown in Fig-
ures 15 and 16.
T he Host Interrupt Pin (INT ) will go HI during the sample pe-
riod in which the Current Count Register underflows. T his
event is referenced to the internal sample period clock which is
not available externally.
CDRQ OUTPUT
CDAK INPUT
DATA7:0
OUTPUTS
RD INPUT
DBEN & DBDIR
OUTPUTS
t
DBDL
t
RDDV
t
DKSU
t
DHD1
ISA BUS
BCLK
t
DKHDB
t
STW
t
DRHD
Figure 13. 8-Bit Mono DMA Read/Capture Cycle
PDRQ
OUTPUT
PDAK
INPUT
DATA7:0
INPUTS
WR INPUT
DBEN
OUTPUTS
t
DBDL
t
DKSU
t
DHD2
ISA BUS
BCLK
t
DKHDA
DBDIR
OUTPUT
HI
t
STW
t
DRHD
t
WDSU
Figure 14. 8-Bit Mono DMA Write/Playback Cycle
CDRQ/
PDRQ
OUTPUTS
CDAK/
PDAK
INPUTS
DATA7:0
RD OR WR
INPUTS
ISA BUS
BCLK
LEFT/LOW
BYTE
RIGHT/HIGH
BYTE
t
BWDN
Figure 15. 8-Bit Stereo or 16-Bit Mono DMA Cycle
CDRQ/ PDRQ
OUTPUTS
CDAK/ PDAK
INPUTS
DATA7:0
RD OR WR
INPUTS
ISA BUS
BCLK
LOW
HIGH
LOW
HIGH
LEFT SAMPLE
RIGHT SAMPLE
t
BWDN
Figure 16. 16-Bit Stereo DMA Cycle
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1846JP-REEL 制造商:Analog Devices 功能描述:
AD1847 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec
AD1847JP 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1847JP-REEL 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
AD1847JST 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec
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