參數(shù)資料
型號: AD1846JP
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 19/28頁
文件大小: 277K
代理商: AD1846JP
AD1846
REV. A
–19–
T est and Initialization R egister (IX A3:0 = 11)
IX A3:0
Data 7
11
COR
Data 6
PUR
Data 5
ACI
Data 4
DRS
Data 3
ORR1
Data 2
ORR0
Data 1
ORL1
Data 0
ORL0
ORL1:0
Overrange Left Detect. T hese bits indicate the overrange on the left input channel. T his bit changes on a sample-by-
sample basis. T his bit is read only.
0
Less than –1 dB underrange
1
Between –1 dB and 0 dB underrange
2
Between 0 dB and +1 dB overrange
3
Greater than +1 dB overrange
Overrange Right Detect. T hese bits indicate the overrange on the right input channel. T his bit changes on a sample-by-
sample basis. T his bit is read only.
0
Less than –1 dB underrange
1
Between –1 dB and 0 dB underrange
2
Between 0 dB and +1 dB overrange
3
Greater than +1 dB overrange
Data Request Status. T his bit indicates the current status of the PDRQ and CDRQ pins of the AD1846.
0
CDRQ and PDRQ are presently inactive (LO)
1
CDRQ or PDRQ are presently active (HI)
Autocalibrate-In-Progress. T his bit indicates the state of autocalibration or a recent exit from Mode Change Enable
(MCE). T his bit is read only.
0
Autocalibration is not in progress
1
Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods
Playback Underrun. T his bit is set when playback data has not arrived from the host in time to be played. As a result, a
midscale value will be sent to the DACs. T his bit changes on a sample by sample basis.
Capture Overrun. T his bit is set when the capture data has not been read by the host before the next sample arrives. T he
sample being read will not be overwritten by the new sample. T he new sample will be ignored. T his bit changes on a
sample by sample basis.
T he occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. T he SOUR bit
is the logical OR of the COR and PUR bits. T his enables a polling host CPU to detect an overrun/underrun condition while checking
other status bits.
ORR1:0
DRS
ACI
PUR
COR
T his register’s initial state after reset is “0000 0000.”
Miscellaneous Control R egister (IX A3:0 = 12)
IX A3:0
Data 7
12
res
Data 6
res
Data 5
res
Data 4
res
Data 3
ID 3
Data 2
ID 2
Data 1
ID 1
Data 0
ID 0
res
ID3:0
Reserved for future expansion. T he bits are read only. Do not write to these bits.
AD1846 Revision ID. T hese four bits define the revision level of the AD1846. T he AD1846 is designated
ID = “1010.” Revisions increment by one LSB. T hese bits are read only.
T his register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use.
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