參數(shù)資料
型號： AD1846JP
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 13/28頁
文件大?。?/td> 277K
代理商： AD1846JP
AD1846
REV. A
–13–
Status R egister (ADR 1:0 = 2)
AD R1:0
2
Data 7
C U/L
Data 6
CL/R
Data 5
CRDY
Data 4
SOUR
Data 3
PU/L
Data 2
PL /R
Data 1
PRDY
Data 0
INT
INT
Interrupt Status. T his sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. T his bit is cleared
by any host write of any value to this register. T he IEN bit of the Pin Control Register determines whether the state of this
bit is reflected on the INT pin of the AD1846. T he only interrupt condition supported by the AD1846 is generated by the
underflow of the DMA Current Count Register.
0
Interrupt pin inactive
1
Interrupt pin active
Playback Data Register Ready. T he PIO Playback Data Register is ready for more data. T his bit should only be used when
direct programmed I/O data transfers are desired. T his bit is read only.
0
DAC data is still valid. Do not overwrite.
1
DAC data is stale. Ready for next host data write value.
Playback Left/Right Sample. T his bit indicates whether the PIO playback data needed is for the right channel DAC or left
channel DAC. T his bit is read only.
0
Right channel needed
1
Left channel or mono
Playback Upper/Lower Byte. T his bit indicates whether the PIO playback data needed is for the upper or lower byte of the
channel. T his bit is read only.
0
Lower byte needed
1
Upper byte needed or any 8-bit mode
Sample Over/Underrun. T his bit indicates that the most recent sample was not serviced in time and therefore either a cap-
ture overrun (COR) or playback underrun (PUR) has occurred. T he bit indicates an overrun for ADC capture and an
underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be determined by
reading COR and PUR. T his bit changes on a sample-by-sample basis. T his bit is read only.
Capture Data Ready. T he PIO Capture Data Register contains data ready for reading by the host. T his bit should only be
used when direct programmed I/O data transfers are desired. T his bit is read only.
0
ADC data is stale. Do not reread the information.
1
ADC data is fresh. Ready for next host data read.
Capture Left/Right Sample. T his bit indicates whether the PIO capture data waiting is for the right channel ADC or left
channel ADC. T his bit is read only.
0
Right channel
1
Left channel or mono
Capture Upper/Lower Byte. T his bit indicates whether the PIO capture data ready is for the upper or lower byte of the
channel. T his bit is read only.
0
Lower byte ready
1
Upper byte ready or any 8-bit mode
T he PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. T he host may access this regis-
ter while the bits are transitioning. T he host read may return a zero value just as these bits are changing, for example. A “1” value
would not be read until the next host access.
PRDY
PL/R
PU/L
SOUR
CRDY
CL/R
CU/L
T his registers’s initial state after reset is “1100 1100.”
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1846JP-REEL 制造商:Analog Devices 功能描述:
AD1847 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec
AD1847JP 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1847JP-REEL 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
AD1847JST 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundPort Stereo Codec
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