
AD1846
REV. A
–16–
Left Auxiliary #2 Input Control (IX A3:0 = 4)
IX A3:0
Data 7
4
L MX 2
Data 6
res
Data 5
res
Data 4
L X 2A4
Data 3
L X 2A3
Data 2
L X 2A2
Data 1
L X 2A1
Data 0
L X 2A0
LX 2A4:0 Left Auxiliary Input #2 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.
LX 2A4:0 = 0 produces a +12 dB gain. LX 2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB.
res
Reserved for future expansion. Always write zeros to these bits.
LMX 2
Left Auxiliary #2 Mute. T his bit, when set to 1, will mute the left channel of the Auxiliary #2 input source. T his bit is set
to “1” after reset.
T his register’s initial state after reset is “1xx0 0000.”
R ight Auxiliary #2 Input Control (IX A3:0 = 5)
IX A3:0
D ata 7
5
RMX 2
D ata 6
res
D ata 5
res
D ata 4
RX 2A4
D ata 3
RX 2A3
D ata 2
RX 2A2
D ata 1
RX 2A1
D ata 0
RX 2A0
RX 2A4:0 Right Auxiliary Input #2 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.
RX 2A4:0 = 0 produces a +12 dB gain. RX 2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB.
res
Reserved for future expansion. Always write zeros to these bits.
RMX 2
Right Auxiliary #2 Mute. T his bit, when set, will mute the right channel of the Auxiliary #2 input source. T his bit is set to
“1” after reset.
T his register’s initial state after reset is “1xx0 0000.”
Left DAC Control (IX A3:0 = 6)
IX A3:0
6
Data 7
L DM
Data 6
res
Data 5
L DA5
Data 4
L DA4
Data 3
L DA3
Data 2
L DA2
Data 1
L DA1
Data 0
L DA0
LDA5:0
Left DAC Attenuate Select. T he least significant bit of this attenuate select represents –1.5 dB. LDA5:0 = 0 produces a
0 dB attenuation. Maximum attenuation is –94.5 dB.
Reserved for future expansion. Always write a zero to this bit.
Left DAC Mute. T his bit, when set to 1, will mute the left DAC output. Auxiliary inputs are muted independently with
the Left Auxiliary Input Control Registers. T his bit is set to “1” after reset.
res
LDM
T his register’s initial state after reset is “1x00 0000.”
R ight DAC Control (IX A3:0 = 7)
IX A3:0
7
Data 7
RDM
Data 6
res
Data 5
RDA5
Data 4
RDA4
Data 3
RDA3
Data 2
RDA2
Data 1
RDA1
Data 0
RDA0
RDA5:0
Right DAC Attenuate Select. T he least significant bit of this attenuate select represents –1.5 dB. RDA5:0 = 0 produces
0 dB attenuation. Maximum attenuation is –94.5 dB.
Reserved for future expansion. Always write a zero to this bit.
Right DAC Mute. T his bit, when set to 1, will mute the right DAC output. Auxiliary inputs are muted independently with
the Right Auxiliary Input Control Registers. T his bit is set to “1” after reset.
res
RDM
T his register’s initial state after reset is “1x00 0000.”