參數(shù)資料
型號(hào)： AD1816AJS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SoundPort Controller
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 37/52頁
文件大?。?/td> 477K
代理商： AD1816AJS
AD1816A
–37–
REV. A
POM
3DD [3:0]
PHONE-OUT Mute. 0 = Unmuted, 1 = Muted.
3D Depth Phat Stereo Enhancement Control. T he LSB represents 6 2/3% phase expansion, 0000 = 0% and
the range is 0% to 100%.
3D Depth Mute. Writing a “1” to this bit has the same affect as writing 0s to 3DD [3:0] bits, and causes
the Phat 3D Stereo Enhancement to be turned off. 0 = Phat Stereo is on, 1 = Phat Stereo is off.
3DDM
[40] RE SE RVE D
7
DE F AUL T = [0x0000]
2
1
6
5
4
3
2
1
0
7
6
5
4
3
0
RES
RES
[41] HARDWARE VOL UME BUT T ON MODIF IE R
7
6
5
4
DE F AUL T = [0xX X 1B]
2
BM [4:0]
3
2
1
0
7
6
5
4
3
1
0
RES
VMU
VUP
VDN
BM [4:0]
VDM
VUP
VMU
T his register contains a Master Volume attenuation offset, which can be incremented or decremented via the Hardware Volume
Pins. T his register is summed with the Master Volume attenuation to produce the actual Master Volume DAC attenuation. A mo-
mentary grounding of greater than 50 ms on the
VOL_UP
pin will cause a decrement (decrease in Attenuation) in this register.
Holding the pin LO for greater than 200 ms will cause an auto-decrement every 200 ms. T his is also true for a momentary ground-
ing of the
VOL_DN
pin. A momentary grounding of both the
VOL_UP
and
VOL_DN
causes a mute and no increment or decre-
ment to occur.
When Muted, an unmute is possible by a momentary grounding of both the
VOL_UP
and
VOL_DN
pins together, a momen-
tary grounding of
VOL_UP
(this also causes a volume increase), a momentary grounding of
VOL_DN
(this also causes a volume
decrease) or a write of “0” to the VI bit in SS [BASE+1].
Button Modifier
Volume Down
Volume Up
Volume Mute
[42] DSP MAILBOX 0
7
6
DE FAULT = [0x0000]
2
5
4
3
2
1
0
7
6
5
4
3
1
0
MB0R [15:8]
MB0R [7:0]
MB0R [15:0]
T his register is used to send data and control information to and from the DSP.
[43] DSP MAILBOX 1
7
6
DE FAULT = [0x0000]
2
5
4
3
2
1
0
7
6
5
4
3
1
0
MB1R [15:8]
MB1R [7:0]
MB1R [15:0]
T his register is used to send data and control information to and from the DSP.
[44] POWE RDOWN AND T IME R C ONT ROL
7
6
5
C PD
RES
PIW
PIR
DE F AUL T = [0x0000]
2
1
RES
4
3
2
1
0
7
6
5
4
3
0
PAA
PDA
PD P
PT B
3D
PD 3D G PSP
RES
DM
T he AD1816A supports a timeout mechanism used in conjunction with the T imer Base Count and T imer Current Count registers
to generate a power-down interrupt. T his interrupt allows software to power down the entire chip by setting the CPD bit. T his
power-down control feature lets users program a time interval from 1 ms to approximately 1.8 hours in 1 ms increments. Five
power-down count reload enable bits are used to reload the T imer Current Count from the T imer Base Count when activity is
seen on that particular channel.
Programming Example: Generate Interrupt if No ISA Reads or Writes occur within 15 Minutes.
1) Write [SSBASE+0] with 0x0C ; Write Indirect address for T IMER BASE COUNT “register 12”
2) Write [SSBASE+2] with 0x28 ; Write T IMER BASE COUNT with (15 min
×
60 sec/min
×
100 ms) = 0x2328; Note: PT B = 1,
timer decrements every 100 ms
3) Write [SSBASE+3] with 0x23 ; Write High byte of T IMER BASE COUNT
4) Write [SSBASE+0] with 0x2C ; Write Indirect address for POWER-DOWN and T IMER CONT ROL register
5) Write [SSBASE+2] with 0x00 ; Write Low byte of POWER-DOWN and T IMER CONT ROL register
6) Write [SSBASE+3] with 0x31 ; Set Enable bits for PIW and PIR
7) Write [SSBASE+0] with 0x01 ; Write Indirect address for INT ERRUPT CONFIG register
8) Write [SSBASE+2] with 0x82 ; Set the T E (T imer Enable) bit
9) Write [SSBASE+3] with 0x20 ; Set the T IE (T imer Interrupt Enable) bit
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