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AD1816A
–24–
REV. A
[Base+0]
Chip Status/Indirect Address
7
6
5
4
3
2
1
0
CRDY
VBL
INADR[5:0]
RESET = [0x00]
INADR [5:0] (RW) Indirect Address for Sound System (SS). T hese bits are used to access the Indirect Registers shown in T able VIII.
All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS Data
Registers, (Base +2) and (Base +3).
VBL
Volume Button Location. When using an EEPROM to configure the PnP state of the AD1816A, this bit determines
whether PQFP Pins 1 and 2 (T QFP Pins 99 and 100) are used for
VOL_UP
and
VOL_DN
or I
2
S0_DAT A and
I
2
S0_LRCLK respectively.
0
I
2
S0_DAT A and I
2
S0_LRCLK
1
VOL_UP
and
VOL_DN
CRDY
(RO) AD1816A Ready. T he AD1816A asserts this bit when AD1816A can accept data.
0
AD1816A not ready
1
AD1816A ready
[Base+1]
Interrupt Status
7
PI
6
5
4
3
2
1
0
SI
CI
T I
VI
DI
RI
GI
RESET = [0x00]
SI
(RO) SoundBlaster generated Interrupt.
0
No interrupt
1
SoundBlaster interrupt pending
(RW) Game Interrupt (Sticky, Write “0” to Clear).
0
No interrupt
1
An interrupt is pending due to Digital Game Port data ready
(RW) Ring Interrupt (Sticky, Write “0” to Clear).
0
No interrupt
1
An interrupt is pending due to a Hardware Ring pin being asserted
(RW) DSP Interrupt (Sticky, Write “0” to Clear).
0
No interrupt
1
An interrupt is pending due to a write to the DIT bit in indirect register [33] bit <13>
(RW) Volume Interrupt (Sticky, Write “0” to Clear).
0
No interrupt
1
An interrupt is pending due to Hardware Volume Button being pressed
(RW) T imer Interrupt. T his bit indicates there is an interrupt pending from the timer count registers. (Sticky,
Write “0” to Clear).
0
No interrupt
1
Interrupt is pending from the timer count register
(RW) Capture Interrupt. T his bit indicates that there is an interrupt pending from the capture DMA count register.
(Sticky, Write “0” to Clear).
0
No interrupt
1
Interrupt is pending from the capture DMA count register
(RW) Playback Interrupt. T his bit indicates that there is an interrupt pending from the playback DMA count
register. (Sticky, Write “0” to Clear).
0
No interrupt
1
Interrupt is pending from the playback DMA count register
GI
RI
DI
VI
T I
CI
PI
[Base+2]
Indirect SS Data Low Byte
7
6
5
4
3
2
1
0
Indirect SS Data [7:0]
RESET = [0xX X ]
[Base+3]
Indirect SS Data High Byte
7
6
5
4
3
2
1
0
Indirect SS Data [15:8]
RESET = [0xX X ]
Indirect SS
Data [15:0]
Indirect Sound System Data. Data in this register is written to the Sound System Indirect Register specified by the
address contained in INDAR [5:0], Sound System Direct Register [Base +0]. Data is written when the Indirect SS
Data High Byte value is loaded.