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| 型號(hào)： | AC164336 |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 67/285頁(yè) |
| 文件大小： | 0K |
| 描述： | MODULE SOCKET FOR PM3 28/44QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模塊/板類(lèi)型： | QFN 插口模塊 |
| 適用于相關(guān)產(chǎn)品： | MPLAB? PM3 |
| 產(chǎn)品目錄頁(yè)面： | 658 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | PIC24HJ64GP502T-I/MM-ND - IC DSPIC MCU/DSP 64K 28-QFN DSPIC33FJ64GP802T-I/MM-ND - IC DSPIC MCU/DSP 64K 28-QFN PIC24HJ64GP502-I/MM-ND - IC PIC MCU FLASH 64K 28-QFN PIC24HJ64GP502-E/MM-ND - IC PIC MCU FLASH 64K 28-QFN PIC24FJ64GA004-E/ML-ND - IC PIC MCU FLASH 64K 44-QFN PIC24FJ64GA002-E/ML-ND - IC PIC MCU FLASH 64K 28-QFN PIC24FJ48GA004-E/ML-ND - IC PIC MCU FLASH 48K 44-QFN PIC24FJ48GA002-E/ML-ND - IC PIC MCU FLASH 48K 28-QFN PIC24FJ32GA004-E/ML-ND - IC PIC MCU FLASH 32K 44-QFN PIC24FJ32GA002-E/ML-ND - IC PIC MCU FLASH 32K 28-QFN 更多... |
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2006 Microchip Technology Inc.
Preliminary
DS70178C-page 157
dsPIC30F1010/202X
14.8
Slope Control
The I2C standard requires slope control on the SDA
and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate con-
trol, if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
14.9
IPMI Support
The control bit IPMIEN enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
14.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should,
in theory, respond with an acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R_W = 0.
The general call address is recognized when the Gen-
eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).
Following a Start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.
If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set, and, on the falling edge of the ninth bit
(ACK bit), the master event interrupt flag (MI2CIF) is
set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific, or a general call address.
14.11 I2C Master Support
As a Master device, six operations are supported.
Assert a Start condition on SDA and SCL.
Assert a Restart condition on SDA and SCL.
Write to the I2CTRN register initiating
transmission of data/address.
Generate a Stop condition on SDA and SCL.
Configure the I2C port to receive data.
Generate an ACK condition at the end of a
received byte of data.
14.12 I2C Master Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic ‘0’. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK bit is received. Start and Stop con-
ditions are output to indicate the beginning and the end
of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device (7
bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic 1. Thus, the first byte trans-
mitted is a 7-bit slave address, followed by a ‘1’ to indi-
cate receive bit. Serial data is received via SDA, while
SCL outputs the serial clock. Serial data is received 8
bits at a time. After each byte is received, an ACK bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
14.12.1
I2C MASTER TRANSMISSION
Transmission of a data byte, a 7-bit address, or the sec-
ond half of a 10-bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the Baud Rate Generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
14.12.2
I2C MASTER RECEPTION
Master mode reception is enabled by programming the
receive enable (RCEN) bit (I2CCON<3>). The I2C
module must be Idle before the RCEN bit is set, other-
wise the RCEN bit will be disregarded. The Baud Rate
Generator begins counting, and, on each rollover, the
state of the SCL pin toggles, and data is shifted in to the
I2CRSR on the rising edge of each clock.
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| AC164337 | 功能描述:插座和適配器 PM3 40L SOCKET MODULE RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164338 | 功能描述:插座和適配器 PM3 Socket Module RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164339 | 功能描述:插座和適配器 MPLAB PM3 Socket Module RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164340 | 功能描述:插座和適配器 MPLAB PM3 Socket Mod for 8LDFN or 20LQFN RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164341 | 功能描述:插座和適配器 MPLAB PM3 Socket Mod for 16l QFN RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
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